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'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/DRIE-Pegasus/nanoetch click here]'''
<!--Checked for updates on 30/7-2018 - ok/jmli -->
<!--Checked for updates on 5/10-2020 - ok/jmli -->
<!--Checked for updates on 4/9-2025 - ok/jmli -->
== Development of continuous nanoetch ==
== Development of continuous nanoetch ==
{{Template:Author-jmli1}}
<!--Checked for updates on 2/02-2023 - ok/jmli -->
The recipes below have been run on 2" wafers with 30/60/90/120/150 nm lines in zep resist. The wafers were crystalbonded to a 4" oxide carrier leaving only a very small fraction (much less than 1% ) of silicon to be etched. If you intend to etch most of the surface of the wafer to create very small posts or ridges (rather than holes or trenches)
The most used one is the nano1.42 recipe - to access the results, click on the bold link in the bottom of the table.




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|[[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch/nano14|Images]]
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|[[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch/nano142|Images]]
|'''[[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch/nano142|Images]]'''
|[[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch/nano143|Images]]
|[[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch/nano143|Images]]
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*[[Specific Process Knowledge/Etch/ICP Metal Etcher|ICP Metal Etch nanoetch]]
 
 
*[[Specific Process Knowledge/Etch/ICP Metal Etcher/silicon/nano|Etch of nanostructures in silicon on the ICP Metal Etcher]]
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch/nano142-pxnano2|Nanoetch contest: DRIE-Pegasus versus ASE (nano1.42 versus pxnano2)]]
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch/nano142-pxnano2|Nanoetch contest: DRIE-Pegasus versus ASE (nano1.42 versus pxnano2)]]


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