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Specific Process Knowledge/Bonding: Difference between revisions

New page: == Choose bonding methode == *Eutectic bonding *Fusion bonding
 
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== Choose bonding methode ==
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*Eutectic bonding
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*Fusion bonding
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==Bonding==
For bonding samples to a carrier wafer in order to enable '''dry etching''', please go [[Specific_Process_Knowledge/Etch/DryEtchProcessing/Bonding|here]].
 
For bonding samples to a carrier wafer for '''UV-lithography''' using automatic coater and developer, please see this process flow: [[media:Process_Flow_ChipOnCarrier.docx‎|Process_Flow_ChipOnCarrier.docx‎]], and refer to the [[Specific_Process_Knowledge/Etch/DryEtchProcessing/Bonding#Bonding|bonding procedure]] for dry etching.
 
== Choose equipment ==
*[[/Imprinter 02|Imprinter 02]]
*[[/Wafer Bonder 02|Wafer Bonder 02]]
*[[Specific Process Knowledge/Thermal Process/C3 Anneal-bond furnace|C3 furnace anneal bond]]
 
== Choose bonding methods in Wafer Bonder 2 ==
 
*[[/Eutectic bonding|Eutectic bonding]]
*[[/Fusion bonding|Fusion bonding]]
*[[/Anodic bonding|Anodic bonding]]
 
== Comparing the three bonding methods in the wafer bonder 2 ==
 
{| border="2" cellspacing="0" cellpadding="2"
 
|-style="background:silver; color:black"
!
![[/Eutectic bonding|Eutectic bonding]]
![[/Fusion bonding|Fusion bonding]]
![[/Anodic bonding|Anodic bonding]]
|-
 
|-style="background:WhiteSmoke; color:black"
!General description
|For bonding two substrates by use of an interphase that makes an eutecticum.
|For bonding two identical materials.
|For bonding Si and Glass.
|-
 
|-style="background:silver; color:black"
!Bonding temperature
|Depending on the eutecticum 310°C to 400°C.
|Depending on defects 50°C to 400°C.
|Depending on the voltage 300°C to 500°C Standard is 400°C.
|-
 
|-style="background:WhiteSmoke; color:black"
!Annealing temperature
|No annealing
|1000°C-1100°C in the anneal bond furnace (C3).
|No annealing
|-
 
|-style="background:silver; color:black"
!Materials possible to bond
|Bonding of substrates is done by use of the eutectica Au/Si, Au/Sn and Au/Sn/Ni
|Si/Si, SiO2/SiO2
|Si/Pyrex (glass)
|-
 
|-style="background:WhiteSmoke; color:black"
!Substrate size
|Up to 4" 
|Up to 4" 
|Up to 4" 
|-
 
|-style="background:silver; color:black"
!Cleaning
|Cleaning by N2.
|Wet chemical cleaning, [[Specific Process Knowledge/Wafer cleaning/IMEC|IMEC]].
|Cleaning by N2. 
|-
 
|-style="background:WhiteSmoke; color:black"
!Backside alignment
|Double side polished wafers.
|Double side polished wafers.
|Not relevant. 
|-
 
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