Specific Process Knowledge/Etch/Etching of Silicon/Si etch using ASE: Difference between revisions
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'''Feedback to this page''': '''[mailto:labadviser@ | '''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/Etching_of_Silicon/Si_etch_using_ASE click here]''' | ||
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==The Bosch process: Etching of silicon== | ==The Bosch process: Etching of silicon== | ||
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*[http://labmanager | *[http://labmanager.dtu.dk/d4Show.php?id=1607&mach=105 The QC procedure for ASE] | ||
*[http://labmanager | *[http://labmanager.dtu.dk/view_binary.php?fileId=1751 The newest QC data for ASE] | ||
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The recipe Iso is the same recipe as Deepetch but without the passivation steps. <br> | The recipe Iso is the same recipe as Deepetch but without the passivation steps. <br> | ||
It has been tested once by Filip Sandborg-Olsen @nanotech. <br> | It has been tested once by Filip Sandborg-Olsen @nanotech. <br> | ||
He etched with 100% load for | He etched with 100% load for 10 min. He got an etch rate of 5.51µm/min | ||
== Process development == | == Process development == | ||
===Etch of nano sized structures=== | ===Etch of nano sized structures=== | ||
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*See pxnano2 and comparison with nanotech on the Pegasus: [[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch/nano142-pxnano2]] | *See pxnano2 and comparison with nanotech on the Pegasus: [[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch/nano142-pxnano2]] | ||
Older work: | Older work: | ||
Three different examples of etch are shown here. The masking material was zep520A (80 nm). | Three different examples of etch are shown here. The masking material was zep520A (80 nm). | ||
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==Etching Si without back side cooling== | |||
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Etching in an ICP as the ASE without backside cooling normally results in heating up the sample to more than 100 degrees Celsius. This can be problematic especially when using resist as a masking material. <br> | Etching in an ICP as the ASE without backside cooling normally results in heating up the sample to more than 100 degrees Celsius. This can be problematic especially when using resist as a masking material. <br> | ||
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This recipe is intended to only for low etch depths that are not very critical with regards to eg. the sidewall profile. For deep etching of silicon you will need to use the bosch process and the coil power. | This recipe is intended to only for low etch depths that are not very critical with regards to eg. the sidewall profile. For deep etching of silicon you will need to use the bosch process and the coil power. | ||
''' Recipe name in the ASE: "1si_rie1" ''' | |||
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! Wafer ID | ! Wafer ID | ||
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|<!--'''Selectivity (resist:Si)'''--> | |<!--'''Selectivity (resist:Si)'''--> | ||
1:4.8 | 1:4.8 | ||
|<!--'''Etch rate in | |<!--'''Etch rate in SiO2'''--> | ||
SRN: | 32 nm/min | ||
SRN:60 nm/min | |||