Specific Process Knowledge/Bonding: Difference between revisions

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==Bonding==

For bonding samples to a carrier wafer in order to enable '''dry etching''', please go [[Specific_Process_Knowledge/Etch/DryEtchProcessing/Bonding|here]].

For bonding samples to a carrier wafer for '''UV-lithography''' using automatic coater and developer, please see this process flow: [[media:Process_Flow_ChipOnCarrier.docx‎|Process_Flow_ChipOnCarrier.docx‎]], and refer to the [[Specific_Process_Knowledge/Etch/DryEtchProcessing/Bonding#Bonding|bonding procedure]] for dry etching.

== Choose equipment ==

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*[[Specific Process Knowledge/Thermal Process/C3 Anneal-bond furnace|C3 furnace anneal bond]]

== Choose bonding methods in ~~EVG NIL~~ ==

== Choose bonding methods in Wafer Bonder 2 ==

*[[/Eutectic bonding|Eutectic bonding]]

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*[[/Anodic bonding|Anodic bonding]]

== Comparing the three bonding methods in the ~~EVG NIL (EVG NIL has been <span style ="color: red"> Decommissioned </span>)~~ ==

== Comparing the three bonding methods in the wafer bonder 2 ==

{| border="2" cellspacing="0" cellpadding="2"

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|-style="background:WhiteSmoke; color:black"

!Substrate size

|Up to ~~6" (aligning only possible for~~ 4" ~~and 6")~~

|Up to 4"

|Up to ~~6" (aligning only possible for~~ 4" ~~and 6")~~

|Up to 4"

|Up to ~~6" (aligning only possible for~~ 4" ~~and 6")~~

|Up to 4"

|-

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|-style="background:WhiteSmoke; color:black"

!IR alignment

!Backside alignment

|Double side polished wafers.