Specific Process Knowledge/Bonding: Difference between revisions

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== Choose bonding method ==
'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Bonding click here]'''
 
'''Unless anything else is stated, everything on this page, text and pictures are made by DTU Nanolab.'''
 
For bonding samples to a carrier wafer in order to enable '''dry etching''', please go [[Specific_Process_Knowledge/Etch/DryEtchProcessing/Bonding|here]].
 
For bonding samples to a carrier wafer for '''UV-lithography''' using automatic coater and developer, please see this process flow: [[media:Process_Flow_ChipOnCarrier.docx‎|Process_Flow_ChipOnCarrier.docx‎]], and refer to the [[Specific_Process_Knowledge/Etch/DryEtchProcessing/Bonding#Bonding|bonding procedure]] for dry etching.
 
== Choose equipment ==
*[[/Imprinter 02|Imprinter 02]]
*[[/Wafer Bonder 02|Wafer Bonder 02]]
*[[Specific Process Knowledge/Thermal Process/C3 Anneal-bond furnace|C3 furnace anneal bond]]
 
== Choose bonding methods in Wafer Bonder 2 ==


*[[/Eutectic bonding|Eutectic bonding]]
*[[/Eutectic bonding|Eutectic bonding]]
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*[[/Anodic bonding|Anodic bonding]]
*[[/Anodic bonding|Anodic bonding]]


===Comparing the three bonding methods in the EVG NIL===
== Comparing the three bonding methods in the wafer bonder 2 ==
{| border="2" cellspacing="0" cellpadding="4" align="center"
 
!.
{| border="2" cellspacing="0" cellpadding="2"  
 
|-style="background:silver; color:black"
!
![[/Eutectic bonding|Eutectic bonding]]
![[/Eutectic bonding|Eutectic bonding]]
![[/Fusion bonding|Fusion bonding]]
![[/Fusion bonding|Fusion bonding]]
![[/Anodic bonding|Anodic bonding]]
![[/Anodic bonding|Anodic bonding]]
|- valign="top"
|-
|'''General description'''
 
|For bonding two substrates by use of an interphase that makes an eutecticum.
|-style="background:WhiteSmoke; color:black"
|For bonding two identical materials.
!General description
|For bonding Si and Glass.
|For bonding two substrates by use of an interphase that makes an eutecticum.  
|-valign="top"
|For bonding two identical materials.
|'''Bonding temperature'''
|For bonding Si and Glass.  
|Depending on the eutecticum 310<math>^o</math>C to 400<math>^o</math>C.
|-
|Depending on defects 50<math>^o</math>C to 400<math>^o</math>C.
 
|Depending on the voltage 300<math>^o</math>C to 500<math>^o</math>C Standard is 400<math>^o</math>C.
|-style="background:silver; color:black"
|-valign="top"
!Bonding temperature
|'''Annnealing temperature'''
|Depending on the eutecticum 310°C to 400°C.  
|Depending on defects 50°C to 400°C.
|Depending on the voltage 300°C to 500°C Standard is 400°C.  
|-
 
|-style="background:WhiteSmoke; color:black"
!Annealing temperature
|No annealing
|1000°C-1100°C in the anneal bond furnace (C3).
|No annealing
|No annealing
|1000<math>^o</math>C in the bond furnace C3
|-
|No annealing
 
|-valign="top"
|-style="background:silver; color:black"
|'''Materials possible to bond'''
!Materials possible to bond
|Bonding of substrates is done by use of the eutectica Au/Si, Au/Sn and Au/Sn/Ni
|Bonding of substrates is done by use of the eutectica Au/Si, Au/Sn and Au/Sn/Ni  
|Si/Si, SiO<math>_2</math>/SiO<math>_2</math>
|Si/Si, SiO2/SiO2
|Si/Pyrex (glass)
|Si/Pyrex (glass)  
|-valign="top"
|-
|'''Substrate size'''
 
|Up to 6" (aligning only possible for 4" and 6")
|-style="background:WhiteSmoke; color:black"
|Up to 6" (aligning only possible for 4" and 6")
!Substrate size
|Up to 6" (aligning only possible for 4" and 6")
|Up to 4"
|-valign="top"
|Up to 4"
|'''Cleaning'''
|Up to 4"  
|Cleaning by N2.
|-
 
|-style="background:silver; color:black"
!Cleaning
|Cleaning by N2.  
|Wet chemical cleaning, [[Specific Process Knowledge/Wafer cleaning/IMEC|IMEC]].
|Wet chemical cleaning, [[Specific Process Knowledge/Wafer cleaning/IMEC|IMEC]].
|Cleaning by N2.
|Cleaning by N2.
|-valign="top"
|-
|'''IR alignment'''
 
|-style="background:WhiteSmoke; color:black"
!Backside alignment
|Double side polished wafers.
|Double side polished wafers.
|Double side polished wafers.
|Double side polished wafers.
|Not relevant.
|Not relevant.
 
|-
|-  
|}


== Choose equipment ==
<br clear="all" />
*[[/EVG NIL|EVG NIL]]
* [[Specific Process Knowledge/Thermal Process/C3 Furnace Anneal Bond|C3 furnace anneal bond]].

Latest revision as of 07:18, 6 February 2023

Feedback to this page: click here

Unless anything else is stated, everything on this page, text and pictures are made by DTU Nanolab.

For bonding samples to a carrier wafer in order to enable dry etching, please go here.

For bonding samples to a carrier wafer for UV-lithography using automatic coater and developer, please see this process flow: Process_Flow_ChipOnCarrier.docx‎, and refer to the bonding procedure for dry etching.

Choose equipment

Choose bonding methods in Wafer Bonder 2

Comparing the three bonding methods in the wafer bonder 2


Eutectic bonding Fusion bonding Anodic bonding
General description For bonding two substrates by use of an interphase that makes an eutecticum. For bonding two identical materials. For bonding Si and Glass.
Bonding temperature Depending on the eutecticum 310°C to 400°C. Depending on defects 50°C to 400°C. Depending on the voltage 300°C to 500°C Standard is 400°C.
Annealing temperature No annealing 1000°C-1100°C in the anneal bond furnace (C3). No annealing
Materials possible to bond Bonding of substrates is done by use of the eutectica Au/Si, Au/Sn and Au/Sn/Ni Si/Si, SiO2/SiO2 Si/Pyrex (glass)
Substrate size Up to 4" Up to 4" Up to 4"
Cleaning Cleaning by N2. Wet chemical cleaning, IMEC. Cleaning by N2.
Backside alignment Double side polished wafers. Double side polished wafers. Not relevant.
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