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==KOH etch - ''Anisotropic silicon etch''==
'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/KOH_Etch click here]'''
[[Image:KOH_4tommer.jpg|300x399px|thumb|KOH etch for 4" wafers: positioned in cleanroom 3]]
 
'''Unless anything else is stated, everything on this page, text and pictures are made by DTU Nanolab.'''
 
'''All links to Kemibrug (SDS) and Labmanager Including APV and QC requires login.'''
 
 
[[index.php?title=Category:Equipment|Etch Wet KOH etch]]
[[index.php?title=Category:Etch (Wet) bath|KOH etch]]
 
==Si etch - ''Anisotropic silicon etch''==
 
KOH belongs to the family of anisotropic Si-etchants based on aqueous alkaline solutions. The anisotropy stems from the different etch rates in different crystal directions. The {111}-planes are almost inert whereas the etch rates of e.g. {100}- and {110}-planes are several orders of magnitude faster.
KOH belongs to the family of anisotropic Si-etchants based on aqueous alkaline solutions. The anisotropy stems from the different etch rates in different crystal directions. The {111}-planes are almost inert whereas the etch rates of e.g. {100}- and {110}-planes are several orders of magnitude faster.


KOH-etching is a highly versatile and cheap way to realize micromechanical structures if you can live with the necessary Si<math>_3</math>N<math>_4</math>- or SiO<math>_2</math> masking materials and the K contamination of the surface. The latter necessitates in most cases a wet post-clean ('7-up' or RCA-clean) if the wafer is to be processed further.
KOH-etching is a highly versatile and cheap way to realize micro mechanical structures if you can live with the necessary Si<sub>3</sub>N<sub>4</sub>- or SiO<sub>2</sub>-masking materials and the potassium contamination of the surface. '''The latter necessitates in most cases a wet post-clean ([[Specific Process Knowledge/Wafer cleaning/7-up & Piranha|'7-up']] or [[Specific Process Knowledge/Wafer cleaning/RCA|RCA-clean]]) if the wafer is to be processed further. we also recommend to rinse the wafers in a 5% HCL solution to remove metal ions from the KOH solution.'''
 
At Danchip we use as a standard a 28 wt% KOH. The etch rate - and the selectivity towards a SiO<math>_2</math>-mask - is depending on the temperature. We normally use T=80 <sup>o</sup>C but may choose to reduce this to e.g. 60 <sup>o</sup>C or 70 <sup>o</sup>C in case of a high-precission timed etch (e.g. defining a thin membrane). In some cases we recommend to saturate the standard 28 wt% KOH with IPA with an etch temperature at T=70 <sup>o</sup>C (reduce evaporation of IPA). One example is for boron etch-stop, where the selectivity towards the boron-doped silicon is improved roughly a factor of 10 compared to the standard etch. Key facts for the two solutions are resumed in the table:


At DTU Nanolab we use as a standard a 28 wt% KOH. The etch rate - and the selectivity towards a SiO<sub>2</sub>-mask - is depending on the temperature. We normally use T=80 <sup>o</sup>C but may choose to reduce this to e.g. 60 <sup>o</sup>C or 70 <sup>o</sup>C in case of a high-precision timed etch (e.g. defining a thin membrane). In some cases we recommend to saturate the standard 28 wt% KOH with IPA with an etch temperature at T=70 <sup>o</sup>C (reduce evaporation of IPA). One example is for boron etch-stop, where the selectivity towards the boron-doped silicon is improved compared to the standard etch. Etching with IPA added to the KOH solution (250ml IPA/1000ml KOH) can be done in KOH fumehood.
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===KOH solutions===


{| border="1" cellspacing="0" cellpadding="4" align="left"
<gallery caption="Different places to do anisotropic wet silicon etch" widths="350px" heights="250px" perrow="3">
!
image:KOH_BHF.JPG|Wetbench 01: Si etch, for Si etch of 4" and 6" wafers using KOH. Positioned in cleanroom D-3.
! 28 wt% KOH
image:KOH_fumehood.JPG|Fume hood 06: Si etch, for Si etch of 4" and 6" wafers using KOH. Positioned in cleanroom D-3. This is used for wafers that are considered dirty.</gallery>
! 28 wt% KOH sat. with IPA
|-
|General description
|
Etch of Si(100)
|
Etch of Si(100) with boron etch-stop
|-
|Chemical solution
|KOH:H<math>_2</math>O  500 g : 1000 ml
|KOH:H<math>_2</math>O:IPA  500 g : 1000 ml : ?? ml
|-
|Process temperature
|60 <sup>o</sup>C
70 <sup>o</sup>C


80 <sup>o</sup>C
'''The user manuals, quality control procedures and results, user APVs, technical information and contact information can be found in LabManager:'''
<!-- remember to remove the type of documents that are not present -->


|
70 <sup>o</sup>C


[http://labmanager.dtu.dk/function.php?module=Machine&view=view&mach=376 Si Etch 1: KOH info page in LabManager],
[http://labmanager.dtu.dk/function.php?module=Machine&view=view&mach=390 Si Etch 2: KOH info page in LabManager],


[http://labmanager.dtu.dk/function.php?module=Machine&view=view&mach=407 Si Etch 3: KOH info page in LabManager]


|-
==Process Information==


|Possible masking materials:
*[[/ProcessInfo#QC|QC info for standard KOH baths]]
|Stoichiometric Si<math>_3</math>N<math>_4</math>
*[[/ProcessInfo#Mixing KOH|How to mix KOH]]
Si-rich Si<math>_3</math>N<math>_4</math>
*[[/ProcessInfo#Backside protection|Backside protection]]
*[[/ProcessInfo#Theory|Crystal orientation dependency]]


PECVD Si<math>_3</math>N<math>_4</math>
==KOH etching baths==
Key facts for the different etch baths available at DTU Nanolab are resumed in the table:
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{| border="2" cellspacing="0" cellpadding="2"


Thermal SiO<math>_2</math>
!colspan="2" border="none" style="background:silver; color:black;" align="center"|Equipment
|
|style="background:WhiteSmoke; color:black"|<b>Si Etch 01: KOH</b>
Photoresist (1.5 µm AZ5214E)
|style="background:WhiteSmoke; color:black"|<b>Si Etch 02: KOH</b>
|style="background:WhiteSmoke; color:black"|<b>Si Etch 03: KOH</b>
|-
!style="background:Silver; color:black;" align="center" width="60" rowspan="2"|Purpose
|style="background:LightGrey; color:black"|
*Etch of Silicon in 28 wt% KOH
|style="background:WhiteSmoke; color:black"|
*Etch of Silicon in 28 wt% KOH
|style="background:WhiteSmoke; color:black"|
*Etch of Silicon in 28 wt% KOH
|style="background:WhiteSmoke; color:black"|
*Etch of Silicon in 28 wt% KOH
The bath is dedicated wafers with metal or otherwise dirty wafers
|-
|style="background:LightGrey; color:black"|Link to safety APV and SDS
|style="background:WhiteSmoke; color:black"|
*:[http://labmanager.danchip.dtu.dk/d4Show.php?id=4964&mach=376 see APV here]
*:[http://kemibrug.dk/KBA/CAS/106882/?show_KBA=1&portaldesign=1 see SDS here]
|style="background:WhiteSmoke; color:black"|
*:[http://labmanager.danchip.dtu.dk/d4Show.php?id=4964&mach=376 see APV here]
*:[http://kemibrug.dk/KBA/CAS/106882/?show_KBA=1&portaldesign=1 see SDS here]
|style="background:WhiteSmoke; color:black"|
*:[http://labmanager.danchip.dtu.dk/d4Show.php?id=4897&mach=407 see APV here]
*:[http://kemibrug.dk/KBA/CAS/106882/?show_KBA=1&portaldesign=1 see SDS here]
|-
! rowspan="8" style="background:silver; color:black" align="center" valign="center" |Performance
|style="background:LightGrey; color:black"|Etch rates in crystalline silicon (100)
|style="background:WhiteSmoke; color:black"|
*0.4 µm/min (60 °C)
*0.7 µm/min (70 °C)
*1.3 µm/min (80 °C)
|style="background:WhiteSmoke; color:black"|
*0.4 µm/min (60 °C)
*0.7 µm/min (70 °C)
*1.3 µm/min (80 °C)
|style="background:WhiteSmoke; color:black"|
*0.4 µm/min (60 °C)
*0.7 µm/min (70 °C)
*1.3 µm/min (80 °C)
|-
|style="background:LightGrey; color:black"|Etch rates in crystalline silicon (110)
|style="background:WhiteSmoke; color:black"|
*2.5 µm/min (80 °C)
|style="background:WhiteSmoke; color:black"|
*2.5 µm/min (80 °C)
|style="background:WhiteSmoke; color:black"|
*2.5 µm/min (80 °C)
|-
|style="background:LightGrey; color:black"|Etch rates in Thermal SiO2
|style="background:WhiteSmoke; color:black"|
*Theoretical values:
*1.2 nm/min (60 °C)
*7.5 nm/min (80 °C)
|style="background:WhiteSmoke; color:black"|
*Theoretical values:
*1.2 nm/min (60 °C)
*7.5 nm/min (80 °C)
|style="background:WhiteSmoke; color:black"|
*Theoretical values:
*1.2 nm/min (60 °C)
*7.5 nm/min (80 °C)
|-
|style="background:LightGrey; color:black"|Etch rates in other oxides
|style="background:WhiteSmoke; color:black"|
.
|style="background:WhiteSmoke; color:black"|
yannickseis@nbi.ku nov. 2017 @80 °C:
*BPSG from PECVD4: 311nm in about 3 min
*Waveguide oxide from PECVD4: 320nm etched in 26 min
*TEOS oxide from furnace: 300nm etched in 11 min
jemafh@nilt 2019-Marts:
*Standard from PECVD3: selectivity 1:100 to Si(100)
|style="background:WhiteSmoke; color:black"|
.
|-
|style="background:LightGrey; color:black"|Etch rates in PECVD SiN
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|See etchrates for PECVD SiN [https://labadviser.nanolab.dtu.dk/index.php?title=Specific_Process_Knowledge/Thin_film_deposition/Deposition_of_Silicon_Nitride/Deposition_of_Silicon_Nitride_using_PECVD/PECVD3:_Low_stress_nitride_testing#DOE_made_to_find_a_good_QC_nitride_recipe_with_low_stress_and_low_KOH_etch_rate_(by_Berit_Herstrøm_@_DTU_Nanolab_2016_Marts) here]
|style="background:WhiteSmoke; color:black"|
|-
|style="background:LightGrey; color:black"|Etch rates in LPCVD Si3N4 and SiN
|style="background:WhiteSmoke; color:black"|
*Etch rates in LPCVD nitrides is very low. Etch selectivities to Si(100) is higher than 1:10.000
|style="background:WhiteSmoke; color:black"|
*Etch rates in LPCVD nitrides is very low. Etch selectivities to Si(100) is higher than 1:10.000
|style="background:WhiteSmoke; color:black"|
*Etch rates in LPCVD nitrides is very low. Etch selectivities to Si(100) is higher than 1:10.000
|-
|style="background:LightGrey; color:black"|Roughness
|style="background:WhiteSmoke; color:black"|
*Typical: 100-600 Å
|style="background:WhiteSmoke; color:black"|
*Typical: 100-600 Å
|style="background:WhiteSmoke; color:black"|
*May be high due to contamination and poor controlled concentration of the KOH solution
|-
|style="background:LightGrey; color:black"|Anisotropy
|style="background:WhiteSmoke; color:black"|
*The etch rate is very dependent on the crystal orientation of the silicon.
|style="background:WhiteSmoke; color:black"|
*The etch rate is very dependent on the crystal orientation of the silicon.
|style="background:WhiteSmoke; color:black"|
*The etch rate is very dependent on the crystal orientation of the silicon.
|-
!style="background:silver; color:black" align="center" valign="center" rowspan="2"|Process parameter range
|style="background:LightGrey; color:black"|Chemical solution
|style="background:WhiteSmoke; color:black"|
*Mixing ratios giving 28 wt% KOH solutions
KOH:H<sub>2</sub>O - 1000 ml: 1200 ml, when using premixed 50% KOH solution
|style="background:WhiteSmoke; color:black"|
*Mixing ratios giving 28 wt% KOH solutions
KOH:H<sub>2</sub>O - 1000 ml: 1200 ml, when using premixed 50% KOH solution
|style="background:WhiteSmoke; color:black"|
*Mixing ratios giving 28 wt% KOH solutions
KOH:H<sub>2</sub>O - 1000 ml: 1200 ml, when using premixed 50% KOH solution
|-
|-
|Etch rate
|style="background:LightGrey; color:black"|Temperature
|
|style="background:WhiteSmoke; color:black"|
~100 nm/min (Pure Al)
*Max 80 °C (standard etch)
|
|style="background:WhiteSmoke; color:black"|
~60(??) nm/min
*Max 80 °C
|style="background:WhiteSmoke; color:black"|
*Max 80 °C
|-
|-
|Batch size
!style="background:silver; color:black" align="center" valign="center" rowspan="4"|Substrates
|
|style="background:LightGrey; color:black"|Batch size
1-25 wafers at a time
|style="background:WhiteSmoke; color:black"|
|
*1-25 wafers at a time  
1-25 wafer at a time
|style="background:WhiteSmoke; color:black"|
*1-25 wafers at a time
|style="background:WhiteSmoke; color:black"|
*1-7 wafers at a time  
|-
|-
|Size of substrate
|style="background:LightGrey; color:black"|Size of substrate
|
|style="background:WhiteSmoke; color:black"|
4" wafers
*4”-6" wafers
|
|style="background:WhiteSmoke; color:black"|
4" wafers
*4”-6" wafers
|style="background:WhiteSmoke; color:black"|
*2” wafers
*4” wafers
*6” wafers
*Small pieces
|-
|-
|Allowed materials
|style="background:LightGrey; color:black"|Allowed materials
|
|style="background:WhiteSmoke; color:black"|
*Aluminium
*Silicon
*Silicon
*Silicon Oxide
*Silicon oxide
*Silicon Nitride
*Silicon (oxy)nitride
*Silicon Oxynitride
|style="background:WhiteSmoke; color:black"|
*Photoresist
*E-beam resist
|
*Aluminium
*Silicon
*Silicon
*Silicon Oxide
*Silicon oxide
*Silicon Nitride
*Silicon (oxy)nitride
*Silicon Oxynitride
|style="background:WhiteSmoke; color:black"|
*Photoresist
*All except for Polymers
*E-beam resist
|-
|style="background:LightGrey; color:black"|Masking material
|style="background:WhiteSmoke; color:black"|
*Stoichiometric Si3N4
*Silicon rich nitride SiN
*PECVD Si3N4
*Thermal SiO2
|style="background:WhiteSmoke; color:black"|
*Stoichiometric Si3N4
*Silicon rich nitride SiN
*PECVD Si3N4
*Thermal SiO2
|style="background:WhiteSmoke; color:black"|
*Stoichiometric Si3N4
*Silicon rich nitride SiN
*PECVD Si3N4
*Thermal SiO2
|-
|-
|}
|}
<sup>{{fn|1}}</sup> Measured by Eric Jensen from DTU-Nanotech, October 2013.
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