Jump to content

Specific Process Knowledge/Etch/Etching of Silicon: Difference between revisions

← Older edit
VisualWikitext
Bghe (talk | contribs)
DCH-Employees-701, NLAB-Employees-701, NLAB-LabmanagerAllUsers, Bureaucrats, Administrators
7,301 edits
Jmli (talk | contribs)
DCH-Employees-701, NLAB-Employees-701, NLAB-LabmanagerAllUsers
4,565 edits
No edit summary
 
(5 intermediate revisions by 3 users not shown)
Line 1: Line 1:
'''Feedback to this page''': '''[mailto:labadviser@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.danchip.dtu.dk/index.php?title=Specific_Process_Knowledge/Etch/Etching_of_Silicon click here]'''
'''Unless anything else is stated, everything on this page, text and pictures are made by DTU Nanolab.'''
<!-- Replace "http://labadviser.danchip.dtu.dk/..." with the link to the Labadviser page-->
 
'''All links to Kemibrug (SDS) and Labmanager Including APV and QC requires login.'''
 
'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php?title=Specific_Process_Knowledge/Etch/Etching_of_Silicon click here]'''
<!-- Replace "http://labadviser.nanolab.dtu.dk/..." with the link to the Labadviser page-->
<!--Page reviewed by jmli 9/8-2022  -->
<!--Checked for updates on 21/10-2025 - ok/jmli -->
   
   
== Comparing silicon etch methods at Danchip ==
== Comparing silicon etch methods ==


There are a broad varity of silicon etch methodes at Danchip. The methodes are compared here to make it easier for you to compare and choose the one that suits your needs.  
There are a broad variety of silicon etch methods at DTU Nanolab The methods are compared here to make it easier for you to compare and choose the one that suits your needs.  


===Wet etches:===
===Wet etches:===
Line 11: Line 17:


===Dry etches:===
===Dry etches:===
*[[/Si etch using RIE1 or RIE2|Si etch using RIE2]]
*[[/Si etch using ASE|Si etch using ASE (Advanced Silicon Etch)]]
*[[/Si etch using ASE|Si etch using ASE (Advanced Silicon Etch)]]
*[[Specific Process Knowledge/Etch/DRIE-Pegasus|Si etch using DRIE-Pegasus (Silicon Etch)]]
*[[Specific Process Knowledge/Etch/DRIE-Pegasus|Si etch using DRIE-Pegasus (Silicon Etch)]]
Line 26: Line 31:
![[Specific Process Knowledge/Etch/KOH Etch|Si Etch]]
![[Specific Process Knowledge/Etch/KOH Etch|Si Etch]]
![[Specific Process Knowledge/Etch/Wet Polysilicon Etch|Wet PolySilicon etch]]
![[Specific Process Knowledge/Etch/Wet Polysilicon Etch|Wet PolySilicon etch]]
![[Specific Process Knowledge/Etch/RIE (Reactive Ion Etch)|RIE (Reactive Ion Etch)]]
![[Specific Process Knowledge/Etch/DRIE-Pegasus|DRIE-Pegasus (Deep Reactive Ion Etch)]]
![[Specific Process Knowledge/Etch/DRIE-Pegasus|DRIE-Pegasus (Deep Reactive Ion Etch)]]
![[Specific Process Knowledge/Etch/ASE (Advanced Silicon Etch)|ASE (Advanced Silicon Etch)]]
![[Specific Process Knowledge/Etch/ASE (Advanced Silicon Etch)|ASE (Advanced Silicon Etch)]]
Line 42: Line 46:
|
|
*Isotropic etch in crystalline silicon and polysilicon
*Isotropic etch in crystalline silicon and polysilicon
|
*Can etch isotropic and anisotropic depending on the process parameters and mask design.
|
|
*State-of-the-art dry silicon etcher with atmospheric cassette loader
*State-of-the-art dry silicon etcher with atmospheric cassette loader
Line 49: Line 51:
*Extremely high etch rate and advanced processing options
*Extremely high etch rate and advanced processing options
|
|
*As RIE but better for high aspect ratio etching and deep etches (higher etch rate)
*Can etch isotropic and anisotropic depending on the process parameters and mask design
*Good selectivity to photoresist
*Good selectivity to photoresist
*The ASE is dedicated to polymer etch, which can affect the Si etch stability.
*The ASE open for same metal on the samples and SiO2 etching, which can affect the Si etch stability.
|
|
*This is dedicated to metal etch. So fare only Si etch of nanostructures has been explored on the system.
*This is dedicated to metal etch. So fare only Si etch of nanostructures has been explored on the system.
Line 64: Line 66:
*Silicon Nitride
*Silicon Nitride
*Silicon Oxide
*Silicon Oxide
|
*Silicon Nitride
*Silicon Oxide
*Photoresist
|
|
*Photo-, DUV- and e-beamresist
*Photo-, DUV- and e-beamresist
Line 106: Line 104:
|
|
*~100-200 nm/min, highly dependent on doping level
*~100-200 nm/min, highly dependent on doping level
|
*<40nm/min to >600nm/min depending on recipe parameters and mask design
|
|
*Up to 18-20 µm/min depending on recipe, mask design and aspect ratio.
*Up to 18-20 µm/min depending on recipe, mask design and aspect ratio.
Line 135: Line 131:
*<nowiki>#</nowiki>1 100 mm wafer
*<nowiki>#</nowiki>1 100 mm wafer
*<nowiki>#</nowiki>1 150 mm wafers (only when the system is set up to 150mm)  
*<nowiki>#</nowiki>1 150 mm wafers (only when the system is set up to 150mm)  
|
*As many small samples as can be fitted on a 100mm wafer
*<nowiki>#</nowiki>1 50 mm wafer fitted on a 100mm wafer
*<nowiki>#</nowiki>1 100 mm wafer
*<nowiki>#</nowiki>1 150 mm wafers (only RIE2 when set up for 150mm)
|
|
*As many small samples as can be fitted on a 150mm wafer
*As many small samples as can be fitted on a 150mm wafer
Line 166: Line 157:
*Silicon Oxynitride
*Silicon Oxynitride
*Photoresist
*Photoresist
|
*Silicon
*Silicon Oxide
*Silicon Nitride
*Silicon Oxynitride
*Photo-, DUV- and e-beamresist
*Other metals if they cover less than 5% of the wafer area (ONLY RIE2!)
*Quartz/fused silica
|
|
*Silicon
*Silicon
Line 190: Line 173:
*Aluminium
*Aluminium
*Quartz/fused silica
*Quartz/fused silica
*Other metals if they cover less than 5% of the wafer area
|
|
*Silicon
*Silicon
Retrieved from "https://labadviser.nanolab.dtu.dk//index.php?title=Specific_Process_Knowledge/Etch/Etching_of_Silicon"