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Content and illustration by Thomas Pedersen @ DTU Nanolab unless otherwise noted.
Content and illustration by Thomas Pedersen, DTU Nanolab unless otherwise noted.


=Pattern preparation for exposure on JEOL 9500 =
=Pattern preparation for exposure on JEOL 9500 =
Prior to exposure a pattern must be prepared for exposure. The original pattern must be provided in GDS format. Depending on requirements and complexity level pattern preparation will involve all or subset of the following steps.  
Prior to exposure a pattern must be prepared for exposure. The original pattern must be provided in GDS format. Depending on requirements and complexity level pattern preparation will involve all or subset of the following steps.  


*Exposure time estimation
*Placement preparation
*Placement preparation
*Alignment preparation
*Alignment preparation
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Some steps are done using Beamer from GenISys GmbH. We advise all users to familiarise themselves with Beamer [https://www.genisys-gmbh.com/webinar-series-beamer-training.html through the tutorial series found on GenISys own website.] or from our own [[Specific_Process_Knowledge/Lithography/EBeamLithography/BEAMER|Beamer guide.]]
Some steps are done using Beamer from GenISys GmbH. We advise all users to familiarise themselves with Beamer [https://www.genisys-gmbh.com/webinar-series-beamer-training.html through the tutorial series found on GenISys own website.] or from our own [[Specific_Process_Knowledge/Lithography/EBeamLithography/BEAMER|Beamer guide.]]


== Placement preparation ==
Please observe that wafers are clamped in such a way that it is not possible to expose the rim of the wafer. The patternable diameter for wafers are as listed below. Writing a pattern outside this area does not damage the tool but it is a waste of time.
Pattern placement is a bit different compared to UV mask design convention and different to how our Heidelberg MLA systems work. Pattern placement is very dependent on the boundary box of the design. All patterns are placed using the '''ARRAY''' command and they are placed with respect to the center of the design boundary box. This is illustrated with the two designs, L1 and L2, below. L1 is a design nicely centered around (0,0) with a symmetric bounding box. If placed by the '''ARRAY''' command with no offset this will come out entirely as expected. L2 is however offset from (0,0) and if exported with its local bounding box and placed by the '''ARRAY''' command with no offset, it will be exposed at the center of the substrate. Thus, it is vital to keep the bounding box in mind as the '''ARRAY command places patterns with respect to the center of the bounding box.''' To get the desired result in this example, one can define an appropriate offset in the '''ARRAY''' command for exposure of L2.
*2": 44 mm
*4": 93 mm
*6": 138 mm


[[File:BoundingBox.png|1000px|center|frameless]]
<br>


== Alignment preparation ==
==Exposure time estimation==
=== Boundary box alignment ===
The writing time should always be estimated prior to an exposure session. The writing time ''t'' [s] is a function of exposure dose ''Q'' [C/cm<sup>2</sup>], pattern area ''A'' [m<sup>2</sup>] and beam current ''I'' [A], can calculated as
In continuation of the example above, if two layers/exposures are to be aligned to each other in subsequent process steps it is vital that the two layers boundary boxes are identical or at least symmetric around (0,0). With reference to the example below, the boundary boxes can be made identical by either
 
''t = QA/I''
 
As a rule of thumb and easy extrapolation, exposure of an area of 1.000.000 µm<sup>2</sup> at 1 nA and exposure dose of 100 µC/cm<sup>2</sup> takes 17 min. A simple Excel sheet to estimate writing time is [[:File:WritingTimeEstimator.xlsx|available here.]] The area can in principle be obtained from the design layout program, some layout programs are however surprisingly poor at giving a correct total area unless the design is very simple. In general the best way to obtain the total area is by importing the design into Beamer and reading the area from the import log or the pattern viewer.
 
<br>
 
== Pattern placement ==
Pattern placement on the JEOL system has a very important difference regarding patttern placement compared to our Heidelberg MLA systems. Pattern placement is entirely dependent on the boundary box of the design. The boundary box is simply defined as the smallest box enclosing the entire design. All patterns are placed using the '''ARRAY''' command and they are placed with respect to the '''center of the design boundary box.''' This is illustrated below with the two designs, L1 and L2. L1 is a design nicely centered around (0,0) with a symmetric bounding box. When placed by the '''ARRAY''' command at (0,0) this will come out entirely as expected. L2 does however not have a bounding box centered around (0,0) and when placed by the '''ARRAY''' command at (0,0), it will be exposed at the center of the substrate. Thus, it is vital to keep the bounding box in mind as the '''ARRAY command places patterns with respect to the center of the bounding box.''' This is in stark contrast to how the MLA UV lithography systems work and it is often essential to intentionally control the bounding box of a pattern.
 
 
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
|-
| [[image:BoundingBox.png|1000px]]
|-
| colspan="1" style="text-align:center;|
Illustration of the importance of the bounding box of a pattern. Patterns are always placed with respect to the center of their bounding box.
|}
 
=== Boundary box control ===
In continuation of the example above, if two layers are to be positioned correctly relative to each other it is vital to control the extend of the boundary box, since '''the ARRAY command places patterns with respect to the center of the bounding box'''. In the example above the bounding box of L2 is not symmetric around the design coordinate system (0,0) and hence it will be moved to the substrate center during exposure, unless the user defines an offset in the '''ARRAY''' command that places the pattern.
 
The bounding box of L2 can be controlled in two ways:


*Letting L2 inherit the L1 boundary box (option in Beamer)
*Letting L2 inherit the L1 boundary box (option in Beamer)
*Placing small corner marks on L2 to force the boundary box as needed
*Placing small corner marks on L2 to force the boundary box as needed


Corner marks can be 1x1 nm boxes placed outside the substrate to avoid having them exposed onto the substrate.
In the example below corner marks are placed symmetric around design system (0,0) on L2 and hence the bounding box of L2 is now symmetric around design (0,0). Corner marks can be 1x1 nm boxes, hencce they will be too small to actually show up in the developed resist pattern.
 
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
|-
| [[image:BoundingBoxAlign.png|1000px]]
|-
| colspan="1" style="text-align:center;|
Illustration of bounding box control by intentionally adding control geometry to force the bounding box to be symmetric around design system (0,0) on L2.
|}
 
== Alignment preparation ==
Alignment on the JEOL 9500 system has a few quirks and pitfalls as a few key elements are not immediately intuitive. The first step to a succesful alignment is proper pattern preparation and understanding how patterns are placed by the system.
 
===Wafer scale and chip array alignment===
There is two fundamentally different approaches to pattern alignment on the JEOL 9500 system. One can either do a wafer scale layout where essentially one design covering all elements of the pattern is exposed, i.e. a 1 by 1 array as defined by the ARRAY command. Or, one can expose chips instanced into an array using the ARRAY command. In the first case the pattern can only be aligned via global alignment to a single set of alignment marks defining the wafer coordinate system. In the second case, an initial wafer alignment is made but each chip can then be individually aligned to an extra set of individual chip alignment marks. This is illustrated below.
 
In the wafer scale layout, L1 is exposed with a set of global alignment marks (P & Q marks) in order to allow alignment of the next wafer scale layer, L2. Thus the placement of L2 is determined entirely by a single set of alignment marks. In the chip array design, in addition to the global alignment marks (P & Q marks) chip alignment marks for each instance of the chip design is also produced. Thus the placement of each instance of L2 is determined by a local mark very close to where the pattern of L2 is actually printed for increased alignment precision.
 
Global alignment using P & Q marks is done using the SETWFR subprogram. The P & Q mark coordinates are defined in the substrate coordinate system (X,Y). For instance, on a 4" wafer it is typical to place the P and Q marks at (-35000,0) and (35000,0), respectively.
 
Chip marks are different however as illustrated in the right most part of the illustration below. Chip mark coordinates refer to the local chip coordinate system (X',Y'). For instance, if a chip design has a size of 800 x 800 µm it would be convenient to place chip alignment marks at M1 = (-500,500), M2 = (500,500), M3 = (500,-500) and M4 = (-500,-500). If using more than one chip mark the order must be as specified in the illustration. The JEOL system supports 1 or 4 mark chip alignment (CHIPAL 1 or CHIPAL 4).


[[File:BoundingBoxAlign.png|1000px|center|frameless]]
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
|-
| [[image:EBL_align.png|1000px]]
|-
| colspan="1" style="text-align:center;|
Illustration of wafer scale pattern alignment and chip array alignment for two designs, L1 and L2.
|}


=== Detection of alignment mark ===
=== Detection of alignment mark ===
If alignment is needed it is vital to consider this already at the process design and mask design level to ensure that a visible mark is produced. Alignment is done using the electron beam in either SEM mode or beam scan mode. In SEM mode the stage is moved to the expected alignment mark position and the user will manually observe the SEM image and adjust stage position to center the mark at as high magnification as required by alignment tolerance of the design. In beam scan mode the user sets up a routine that will scan the beam across the expected mark position and the Backscatter Electron Detector (BED) will detect the backscattered signal. This is done in both x- and y-directions and system will calculate the mark center based on this.
If alignment is needed it is vital to consider this already at the process design and mask design level to ensure that a visible mark is produced. Alignment is done using the electron beam in either SEM mode or beam scan mode. It is vital that the mark produced is visible in a 100 kV SEM or from a 100 kV beam scan. For this purpose marks made by heavy metals or etched trences with an aspect rate of at least 1 is preferable. In SEM mode the stage is moved to the expected alignment mark position and the user will manually observe the SEM image and adjust stage position to center the mark at as high magnification as required by alignment tolerance of the design. In beam scan mode the user sets up a routine that will scan the beam across the expected mark position and the Backscatter Electron Detector (BED) will detect the backscattered signal. This is done in both x- and y-directions and the system will calculate the mark center based on the second derivative of the backscatter signal.


[[File:JEOL9500Alignment.png|700x700px|center|frameless|Alignment modes of JEOL 9500.]]
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
|-
| [[image:JEOL9500Alignment.png|800px]]
|-
| colspan="1" style="text-align:center;|
Illustration of SEM mode alignment and beam scan alignment.
|}


The advantage of SEM mode is that it is fairly straight forward to do. It is however also very slow as it requires constant user input to move the stage at higher and higher magnification levels until position is sufficiently determined. Due to the time it takes it is hardly realistic to do chip alignment, only global wafer alignment should be done in this way.
The advantage of SEM mode is that it is fairly straight forward to do. It is however also very slow as it requires constant user input to move the stage at higher and higher magnification levels until position is sufficiently determined. Due to the time it takes it is hardly realistic to do chip alignment, only global wafer alignment should be done in this way.
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[[File:9500MarkScan4.png|800px|center|frameless]]
[[File:9500MarkScan4.png|800px|center|frameless]]
==Fracturing==
Pattern fracturing is an essential part of the pattern preparation process. Pattern fracturing will automatically happen at either Proximity Effect Correction in Beamer or upon export to V30. If one does not actively change fracturing parameters it will be done with default parameters which can work great in many cases. For best possible result it can however be necessary to actively control how the pattern is fractured, how beam shots are placed to form the pattern and what order pattern elements are written in. This can all be controlled with the ''Fracture'' node in Beamer and hence in combination with the ''PEC'' node it is one of the most impactful nodes. In this section we will illustrate some of the issues that the ''Fracture'' node can help mitigate. For information on the ''Fracture'' node in Beamer, please refer to the Beamer guide.
For precise control of critical dimension (CD) for small features it is important to consider the actual beam size and how it is placed, i.e. how the shapes are filled with beam shots. This is illustrated in the three shapes below. The left shape is 25 x 25 nm and written with a 5 nm beam spot. This works very well. However, if one wishes to write a 28 x 28 nm shape under the same circumstances shot filling becomes an issue. Similarly in the right hand shape, any shape that has a sloped edge will have shot filling issues. It is obvious that these issues are only a concern when CD control on a sub beam size level is needed.
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
|-
| [[image:ShotFilling.png|800px]]
|-
| colspan="1" style="text-align:center;|
Illustration of shot filling issues for small shapes.
|}


== Bulk and sleeve separation - double current exposure ==
== Bulk and sleeve separation - double current exposure ==
Patterns that contain a mix of fine and large dimension structures can advantageously be broken into a low current and a high current exposure. In this way the fine features can be written at low current (and low speed) and the large structures can be written at high current (and high speed). Some patterns, for instance a fine electrode pattern with large bonding pads, can easily and manually be broken into a fine and coarse part and placed in two different layers. For many patterns this can however be very cumbersome but the process can also be automated with Beamer using "bulk and sleeve" setup.  The concept is illustrated below. In this setup, Beamer will extract the periphery (sleeve) of a pattern into one layer and the bulk of structures into another layer. The bulk is oversized slightly (adding a bias) to ensure overlap between the two patterns at exposure. In this way structures can be defined with best possible edge definition while keeping exposure time down. [https://labmanager.dtu.dk/view_binary.php?fileId=5412 A Beamer flow with a default bulk and sleeve setup can be found here.] A 200 nm sleeve with a 50 nm overlap is a good starting point.
Patterns that contain a mix of fine and large dimension structures can advantageously be broken into a low current and a high current exposure. In this way the fine features can be written at low current (and low speed) and the large structures can be written at high current (and high speed). Some patterns, for instance a fine electrode pattern with large bonding pads, can easily and manually be broken into a fine and coarse part and placed in two different layers. For many patterns this can however be very cumbersome but the process can also be automated with Beamer using "bulk and sleeve" setup.  The concept is illustrated below. In this setup, Beamer will extract the periphery (sleeve) of a pattern into one layer and the bulk of structures into another layer. The bulk is oversized slightly (adding a bias) to ensure overlap between the two patterns at exposure. In this way structures can be defined with best possible edge definition while keeping exposure time down. [https://labmanager.dtu.dk/view_binary.php?fileId=5412 A Beamer flow with a default bulk and sleeve setup can be found here.] A 500 nm sleeve with a 200 nm overlap is a good starting point.




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*Use a nummerical PSF
*Use a nummerical PSF


The pre-computed PSF can be loaded from either a separate file, from the local archive or from the global archive. In any case the file will probably originate from a Tracer simulation, for more on this visit our [[Specific_Process_Knowledge/Lithography/EBeamLithography/TRACER|Tracer page.]] It can be advantageus to place your PSF in the global (network) archive such that it is available on the Beamer PC in the cleanroom as well as the Beamer PC outside the cleanroom.  
The pre-computed PSF can be loaded from either a separate file, from the local archive or from the global archive. In any case the file will probably originate from a Tracer simulation. It can be advantageus to place your PSF in the global (network) archive such that it is available on the Beamer PC in the cleanroom as well as the Beamer PC outside the cleanroom.  


A guassian approximation is mostly useful if trying to replicate a result from litterature or if one has worked deliberately towards determining the gaussian constants for a particular process.
A guassian approximation is mostly useful if trying to replicate a result from litterature or if one has worked deliberately towards determining the gaussian constants for a particular process.