Jump to content

Specific Process Knowledge/Thermal Process/E1 Furnace Oxidation (8"): Difference between revisions

Paphol (talk | contribs)
Pevo (talk | contribs)
 
(18 intermediate revisions by 2 users not shown)
Line 1: Line 1:
=<span style="background:#FF2800">THIS PAGE IS UNDER CONSTRUCTION</span>[[image:Under_construction.png|200px]]=
'''Feedback to this page''': '''[mailto:thinfilm@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php?title=Specific_Process_Knowledge/Thermal_Process/E1_Furnace_Oxidation_(8%22) click here]'''


'''Feedback to this page''': '''[mailto:thinfilm@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php?title=Specific_Process_Knowledge/Thermal_Process/E1_Furnace_Oxidation_(8%22) click here]'''
''This page is written by DTU Nanolab  internal''


[[Category: Equipment |Thermal C1]]
[[index.php?title=Category:Equipment|Thermal C1]]
[[Category: Thermal process|C1]]
[[index.php?title=Category:Thermal process|C1]]
[[Category: Furnaces|C1]]
[[index.php?title=Category:Furnaces|C1]]




==Oxidation (8") furnace (E1)==
==Oxidation (8") furnace (E1)==
[[Image:C1.JPG|thumb|300x300px|Anneal-oxide furnace (C1). Positioned in cleanroom E-6]]
[[Image:E1_furnace.JPG|thumb|300x300px|Oxidation (8") furnace (E1). Positioned in cleanroom E-6. ''Photo: DTU Nanolab internal'']]
 
The Oxidation (8") furnace (E1) is a Tempress horizontal furnace for oxidation and annealing of silicon wafers.


The Oxidation (8") furnace (E1) is a Tempress horizontal furnace for oxidation and annealing of silicon wafers. Both 150 mm and 200 mm wafers can be processed in the furnace.
Both 150 mm and 200 mm wafers can be processed in the furnace. 100 mm wafers can also be processed in the furnace, but they should normally go in one of the other furnaces in the cleanroom instead. To switch between different wafer sizes, the furnace responsible persons will have to change the quartz boats in the furnace.


The Oxidation (8") furnace is the top furnace tube in the E-stack furnaces, which positioned in cleanroom E-6. Most of wafers have to be RCA cleaned, before they enter the furnace. The only exceptions are brand new wafers, wafers from the A-stack furnaces, wafers from C1 furnace, wafers from the LPCVD furnaces (B- and E-stack furnaces) and wafers from PECVD4. Please check the cross contamination information in LabManager, before you use the furnace.  
The Oxidation (8") furnace is the top furnace tube in the furnace E-stack, which in positioned in cleanroom E-6. New silicon wafers bought from DTU Nanolab can go directly into the furnace. Wafers from the A-stack furnaces, the C1 furnace, the LPCVD furnaces (B- and other E-stack furnaces) and from PECVD4 (not III-V materials) can also go directly into the furnace. All processed wafers have to be RCA cleaned, before they enter the furnace. Please check the cross contamination information in LabManager, before you use the furnace.  


Oxygen is using as oxidant for dry oxidation, and for wet oxidation wafer vapour generated by a steamer is used as oxidant. The oxidation recipes on the furnace are named e.g. "WET1000" and "DRY1000", where "WET" or "DRY" indicates whether it is a wet or dry oxidation process, and the number indicates the oxidation temperature.  
Oxygen is used as oxidant for dry oxidation, and for wet oxidation water vapour generated by a Bronkhorst steamer is used as oxidant. The oxidation recipes on the furnace are named e.g. "WET1000" and "DRY1000", where "WET" or "DRY" indicates whether it is a wet or dry oxidation process, and the number indicates the oxidation temperature.  


Annealing can be done for silicon wafers with layers of e.g. silicon oxide, silicon nitride, polysilicon or BPSG glass (deposited in PECVD4). The annealing recipes are named e.g. "ANN1000" (for annealing at 1000 <sup>o</sup>C).
Annealing can be done for silicon wafers with layers of e.g. silicon oxide, silicon nitride, polysilicon or BPSG glass (deposited in PECVD4). The annealing recipes are named e.g. "ANN1000" (for annealing at 1000 <sup>o</sup>C).
Line 37: Line 39:
!style="background:silver; color:black;" align="center"|Purpose  
!style="background:silver; color:black;" align="center"|Purpose  
|style="background:LightGrey; color:black"|
|style="background:LightGrey; color:black"|
*Oxidation of 150 mm and 200 mm wafers
*Oxidation of (100 mm), 150 mm and 200 mm wafers
*Annealing of 150 mm and 200 mm wafers
*Annealing of (100 mm), 150 mm and 200 mm wafers
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
Annealing:
Annealing:
*Using N<sub>2</sub>  
*Using N<sub>2</sub>  
Oxidation:
Oxidation:
*Dry oxidation using O<sub>2</sub>  
*Dry oxidation using O<sub>2</sub>. Reaction: Si + O<sub>2</sub> -> SiO<sub>2</sub>
*Wet oxidation using DI Water steam injection system ( Bronkhorst)
*Wet oxidation using water vapour/steam. Reaction: Si + 2H<sub>2</sub>O -> SiO<sub>2</sub> + 2H<sub>2</sub>(g). The steam is generated by a Bronkhorst steamer injection system.
|-
|-
!style="background:silver; color:black" align="center"|Performance
!style="background:silver; color:black" align="center"|Performance
|style="background:LightGrey; color:black"|Film thickness
|style="background:LightGrey; color:black"|Film thickness and quality
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*Dry SiO<sub>2</sub>: ~ 0 nm  to 300 nm (it takes too long to grow a thicker dry oxide layers)
*Dry oxide: ~ 0 nm  to 300 nm (it takes too long to grow thicker dry oxide layers)
*Wet SiO<sub>2</sub>: ~ 0 nm to 3 µm (23 hours wet oxidation at 1100 <sup>o</sup>C)
*Wet oxide: ~ 0 nm to 3 µm (~23 hours wet oxidation at 1100 <sup>o</sup>C)
* [[Specific Process Knowledge/Thermal Process/Oxidation/Breakdown voltage measurements/E1 furnace break-down voltage measurement results|Break-down voltage measurement results]]
|-
|-
!style="background:silver; color:black" align="center" valign="center" rowspan="3"|Process parameter range
!style="background:silver; color:black" align="center" valign="center" rowspan="3"|Process parameter range
|style="background:LightGrey; color:black"|Process Temperature
|style="background:LightGrey; color:black"|Process Temperature
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*800-1100 <sup>o</sup>C
*800 <sup>o</sup>C - 1100 <sup>o</sup>C
|-
|-
|style="background:LightGrey; color:black"|Process pressure
|style="background:LightGrey; color:black"|Process pressure
Line 63: Line 66:
|style="background:LightGrey; color:black"|Gas flows
|style="background:LightGrey; color:black"|Gas flows
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*N<sub>2</sub>: 0-10 slm  
*N<sub>2</sub>: 0 - 30 slm  
*O<sub>2</sub>: 0-10 slm
*O<sub>2</sub>: 0 - 30 slm
*Steamer flow : 0-12.5 slm (Standard recipe is set at 9.5 slm )  
*Steamer flow: 0 - 12.5 slm (9.5 slm in standard recipes)  
|-
|-
!style="background:silver; color:black" align="center" valign="center" rowspan="2"|Substrates
!style="background:silver; color:black" align="center" valign="center" rowspan="2"|Substrates
|style="background:LightGrey; color:black"|Batch size
|style="background:LightGrey; color:black"|Batch size
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*1-30 100 mm or 150 mm wafers (or 50 mm wafers)
*(100 mm wafers - 1-50 wafers)
*150 mm wafers - 1-50 wafers
*200 mm wafers - 1-25 wafers
|-
|-
| style="background:LightGrey; color:black"|Substrate materials allowed
| style="background:LightGrey; color:black"|Substrate materials allowed
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*New silicon wafers  
*New silicon wafers  
*Silicon wafers with layers of silicon oxide or silicon nitride (RCA cleaned)
*Silicon wafers with layers of silicon oxide or silicon nitride (processed wafers should be RCA cleaned)
*Wafers from the LPCVD furnaces  
*Wafers from A-stack furnaces
*Wafers from PECVD4
*Wafers from C1 furnace
*Wafers from the LPCVD furnaces (B- and other E-stack furnaces)
*Wafers from PECVD4 (not III-V materials)
|-  
|-  
|}
|}