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'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/DRIE-Pegasus/processC click here]'''
<!--Checked for updates on 14/5-2018 - ok/jmli -->
== Process C ==
== Process C ==
{{contentbydryetch}}
<!--Checked for updates on 2/02-2023 - ok/jmli -->
<!--Checked for updates on 4/9-2025 - ok/jmli -->


Process C is labelled Nano silicon etch. In the acceptance test the process was run on a 100 mm Danchip wafer with a test pattern of a series of lines and dots with sizes ranging from 30 nm to 300 nm. The etch load was extremely high, approaching 100 %.
Process C is intended to be used on features in the sub 2-3 µm range. The recipe was run on a 100 mm Nanolab wafer with a test pattern of a series of lines and dots with sizes ranging from 30 nm to 300 nm. The etch load was extremely high, approaching 100 %.


The 100 mm wafers had an Al mask made by lift-off:
The 100 mm wafers had an Al mask made by lift-off:
# 80 nm of spin coated ZEP520A E-beam resist
# 80 nm of spin coated ZEP520A E-beam resist
# Patterned by E-beam lithograph
# Patterned by E-beam lithography
# 20 nm Al deposited and patterned by lift-off
# 20 nm Al deposited and patterned by lift-off
# ~ 99 % etch load
# ~ 99 % etch load
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! Average result  
! Average result  
|-
|-
! Etch rate (µm/min)   
! Etch rate (nm/min)   
| Not specified
| Not specified
|  
|  
|-
|-
! Etched depth (µm)
! Etched depth (nm)
| 300
| 300
|  
|  
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|-
|-
! Selectivity to resist  
! Selectivity to resist  
| Not speicified
| Not specified
|  
|  
|-
|-
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|-
|-
! Common  
! Common  
| colspan="4" | Temperature 10 degs, HBC 10 torr, long funnel, with baffle & 100 mm spacers
| colspan="4" | Temperature 10 degsree, HBC 10 torr, long funnel, with baffle & 100 mm spacers
|}
|}
<gallery>
Image:c1 30 nm dots.jpg
Image:c1 50 nm dots 2.jpg
Image:r1 300 nm dots 1.jpg
</gallery>
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