Jump to content

Specific Process Knowledge/Lithography/EBeamLithography/Cassettes: Difference between revisions

← Older edit
VisualWikitext
Thope (talk | contribs)
DCH-Employees-701, NLAB-Employees-701, NLAB-LabmanagerAllUsers, NLAB-Nlab347-labadviser-users-35231
2,178 edits
Thope (talk | contribs)
DCH-Employees-701, NLAB-Employees-701, NLAB-LabmanagerAllUsers, NLAB-Nlab347-labadviser-users-35231
2,178 edits
 
(31 intermediate revisions by the same user not shown)
Line 20: Line 20:
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
|-
|-
| [[image:BSPCL-520.png|1200px]]
| [[image:BSPCL-520.png|1000px]]
|-  
|-  
| colspan="1" style="text-align:center;|
| colspan="1" style="text-align:center;|
Back side (left )and front side view (right) of the 4" wafer titanium cassette (BSPCL-520).
Back side (left )and front side view (right) of the 4" wafer titanium cassette (BSPCL-520).
|}
== Stage position and cassette orientation==
The stage control window indicates where the stage is currently placed. It indicates this position with a coordinate and a small, red indicator inside the blue box, as illustrated below. Sadly, the system does not indicate how the cassette or cassette slots are placed, thus we have provided an approximate illustration of this below. This can be used as a sanity check to verify that the system is working on the correct cassette slot. In the example below, slot A of the chips cassette is being exposed. Similar illustrations for other cassettes are provided in the cassettes overview table further down this page.
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
|-
| [[image:StageControlWindow.png|500px]] || [[image:StagePos.png|400px]]
|-
| colspan="2" style="text-align:enter;|
Left: The stage position is indicated by the red dot inside the blue square. Right: Example of cassette and slot placement relative to the blue square in the Stage Control Window.
|}
|}


Line 46: Line 57:
The substrate must overlap at least 0.5 mm on both sides of the slot. Hence the height of a chip must be at least 1 mm larger than the slot height, i.e. in order to use slot 3B the chip height must be at least 13.0 mm.
The substrate must overlap at least 0.5 mm on both sides of the slot. Hence the height of a chip must be at least 1 mm larger than the slot height, i.e. in order to use slot 3B the chip height must be at least 13.0 mm.


As the smaller slots are quite narrow and suffer from a significant y-axis offset, it can be necessary to apply an offset for correct placement. The offset indicated below is the observed offset, hence to counter it one must apply a y-axis offset in the opposite direction.
==Wafer exposable area==
As the wafer is clamped to the cassette a small portion along the circumference is covered by the cassette and hence this part is not exposable. The exposable diameter for round wafers are:
*2": 44 mm
*4": 93 mm
*6": 138 mm


== Cassette overview ==
== Cassette overview ==
The table below provides details on all available cassettes.
Users of the chip cassettes should notice that there is a significant y-axis offset between the slot center positions and the actual stage position. The measured offsets are indicated in the table. As seen, they are all negative and hence users should apply a positive y-axis offset in order to get the pattern exposed correctly in the center of the slot/substrate.
There is also a minor shift between the pre-aligner coordinates and the actual stage coordinates. These are indicated in the last column. In order to hit the alignment mark on the first scan users should add this offset to the P-mark offset found on the pre-aligner.
{| class="wikitable"
{| class="wikitable"
|+  Cassette overview
|+  Cassette overview
|-
|-
! Substrate size !! ID !! Slot ID !! Material !! Image !! Slot center coordinates [µm] !! Approximate offset [µm]
! Substrate size !! ID !! Slot ID !! Material !! Image !! Position indication !! Approximate offset [µm] !! PA to stage shift [µm]
|-
|-
| Chips || BM4P-509 || 3A, 3B, 3C, 3D || Ti || [[image:BM4P-509_cas.png|800px]] || 3A: (80.000, 60.000)
| Chips || BM4P-509 || 3A, 3B, 3C, 3D || Ti || [[image:BM4P-509_cas.png|600px]] || [[image:BM4P-509 small.png|300px]]
3B: (200.000, 60.000)


3C: (80.000, 180.000)
|| 3A: -810 µm
 
3D: (200.000, 180.000)
 
|| 2024-01-05
 
3A: -810 µm


3B: -780 µm
3B: -780 µm
Line 68: Line 86:
3C: -840 µm
3C: -840 µm


3D: -975 µm
3D: -975 µm  
 
||


|-
|-
| Chips || BM4P-510 || 3A, 3B, 3C, 3D || Ti || [[image:BM4P-510_cas.png|800px]] || 3A: (80.000, 60.000)
| Chips || BM4P-510 || 3A, 3B, 3C, 3D || Ti || [[image:BM4P-510_cas.png|600px]] || [[image:BM4P-509 small.png|300px]] ||
3B: (200.000, 60.000)
 
3C: (80.000, 180.000)
 
3D: (200.000, 180.000)


|-
|-
| 2" || BM6P-006 || 2A, 2B, 2C, 2D, 2E, 2F || Al || [[image:BM6P-006_cas.png|800px]] || 2A: (80.000. 40.000)
| 2" || BM6P-006 || 2A, 2B, 2C, 2D, 2E, 2F || Al || [[image:BM6P-006_cas.png|600px]] || [[image:BM6P-502 small.png|300px]] ||
2B: (200.000. 40.000)
 
2C: (80.000. 120.000)
 
2D: (200.000. 120.000)
 
2E: (80.000. 200.000)
 
2F: (200.000. 200.000)
|-
|-
| 2" || BM6P-502 || 2A, 2B, 2C, 2D, 2E, 2F || Ti || [[image:BM6P-502_cas.png|800px]] || 2A: (80.000. 40.000)
| 2" || BM6P-502 || 2A, 2B, 2C, 2D, 2E, 2F || Ti || [[image:BM6P-502_cas.png|600px]] || [[image:BM6P-502 small.png|300px]] ||
2B: (200.000. 40.000)
 
2C: (80.000. 120.000)
 
2D: (200.000. 120.000)
 
2E: (80.000. 200.000)
 
2F: (200.000. 200.000)
|-
|-
| 3" || BM4P-021 || 3A, 3B, 3C, 3D || Al || [[image:BM4P-021_cas.png|800px]] || 3A: (80.000, 60.000)
| 3" || BM4P-021 || 3A, 3B, 3C, 3D || Al || [[image:BM4P-021_cas.png|600px]] || [[image:BM4P-509 small copy.png|300px]] ||
3B: (200.000, 60.000)
 
3C: (80.000, 180.000)
 
3D: (200.000, 180.000)


|-
|-
| 3" || BM4P-025 || 3A, 3B, 3C, 3D || Al || [[image:BM4P-025_cas.png|800px]] || 3A: (80.000, 60.000)
| 3" || BM4P-025 || 3A, 3B, 3C, 3D || Al || [[image:BM4P-025_cas.png|600px]] || [[image:BM4P-509 small copy.png|300px]] ||
3B: (200.000, 60.000)
 
3C: (80.000, 180.000)
 
3D: (200.000, 180.000)


|-
|-
| 4" || BSPCL-520 || 4A, 4B, 4C || Ti || [[image:BSPCL-520_cas.png|800px]] || 4A: (90.000, 55.000)
| 4" || BSPCL-520 || 4A, 4B, 4C || Ti || [[image:BSPCL-520_cas.png|600px]] || [[image:BSPCL-520 small.png|300px]] || Currently out of use
4B: (210.000, 55.000)
 
4C: (150.000, 185.000)


|-
|-
| 4" || BM2P-011 || 4D, 4E || Al || [[image:BM2P-011_cas.png|800px]] || 4D: (190.000, 65.000)
| 4" || BM2P-011 || 4D, 4E || Al || [[image:BM2P-011_cas.png|600px]] || [[image:BM2P-011 small.png|300px]] || || 4D: (330,150)
4E: (100.000, 175.000)


|-
|-
| 6" || BW6-009 || 6A || Al || [[image:BW6-009.png|800px]] || 6A: (140.000, 120.000)
| 6" || BW6-009 || 6A || Al || [[image:BW6-009.png|600px]] || [[image:BW6-009 small.png|300px]] ||
|-
|-
| 6" || BW6-042 || 6A || Al || [[image:BW6-042_cas.png|800px]] || 6A: (140.000, 120.000)
| 6" || BW6-042 || 6A || Al || [[image:BW6-042_cas.png|600px]] || [[image:BW6-009 small.png|300px]] ||
|-
|-
| 8" || BSPCL-514 || 8A || Ti || [[image:BPSPCL-514_cas.png|800px]] || 8A: (189.000, 73.500)
| 8" || BSPCL-514 || 8A || Ti || [[image:BPSPCL-514_cas.png|600px]] || [[image:BW6-009 small.png|300px]] ||
|-
|-
| Mask || B6025-025 ||  || Ti || [[image:B6025-025.png|800px]] || (140.000, 120.000)
| Mask || B6025-025 ||  || Ti || [[image:B6025-025.png|600px]] || (140.000, 120.000) ||
|}
|}
Retrieved from "https://labadviser.nanolab.dtu.dk//index.php?title=Specific_Process_Knowledge/Lithography/EBeamLithography/Cassettes"