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'''Feedback to this page:  
'''Feedback to this page:  
[mailto:labadviser@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.danchip.dtu.dk/index.php/Specific_Process_Knowledge/Etch/DRIE-Pegasus click here]'''
[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/DRIE-Pegasus click here]'''
[[Category: Equipment |Etch DRIE]]
[[Category: Equipment |Etch DRIE]]
[[Category: Etch (Dry) Equipment|DRIE]]
[[Category: Etch (Dry) Equipment|DRIE]]
{{contentbydryetch}}
<!--Checked for updates on 28/6-2023 - ok/jmli -->


= DRIE-Pegasus 1=
= DRIE-Pegasus 1=


[[Image:DRIE-Pegasus.jpg |frame|left|x300px|The DRIE-Pegasus 1 load lock and cassette loader in the Danchip cleanroom A-1]]
[[Image:DRIE-Pegasus.jpg |frame|left|x300px|The DRIE-Pegasus 1 load lock and cassette loader in the Nanolab cleanroom A-1. {{photo1}} ]]


'''The user manual(s), quality control procedure(s) and results, user APV(s), technical information and contact information can be found in LabManager:'''
'''The user manual(s), quality control procedure(s) and results, user APV(s), technical information and contact information can be found in LabManager:'''


Equipment info in [http://labmanager.danchip.dtu.dk/function.php?module=Machine&view=view&mach=265| LabManager]
Equipment info in [http://labmanager.dtu.dk/function.php?module=Machine&view=view&mach=265| LabManager]


== Process information ==
== Process information ==


'''SPTS process notation'''
Describing a process recipe on the Pegasus may sometimes be difficult because of the great flexibility of the instrument. A compact and precise notation is therefore required for the recipes. Click [[Specific_Process_Knowledge/Etch/DRIE-Pegasus/Notation|here]] to find a short description of the official SPTS notation.


'''[[Specific Process Knowledge/Etch/DRIE-Pegasus/StandardRecipes|Standard recipes]]'''
'''[[Specific Process Knowledge/Etch/DRIE-Pegasus/StandardRecipes|Standard recipes]]'''
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'''Other etch processes'''
=== Other etch processes ===


*[[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch|Nanostructure etches including nano1.42]]
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/DREM| DREM processes]]
 
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch|Continuous nanostructure etches including nano1.42]]


*[[Specific Process Knowledge/Etch/DRIE-Pegasus/DUVetch|Etch processes with DUV masks]]
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/DUVetch|Etch processes with DUV masks]]
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/Barc|BARC etches]]


*[[Specific Process Knowledge/Etch/DRIE-Pegasus/Isotropic|Isotropic etches]]
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/Isotropic|Isotropic etches]]


More processes, such as for DUV resist, are currently being developed, but they are not quite 'ready for publication' at LabAdviser so please contact Jonas (mailto:jml@danchip.dtu.dk) for more information.
More processes, such as for DUV resist, are currently being developed, but they are not quite 'ready for publication' at LabAdviser so please contact Jonas ([mailto:jmli@dtu.dk jmli@dtu.dk]) for more information.


  <!--  *[[Specific Process Knowledge/Etch/DRIE-Pegasus/slopedsidewalls|Etches that produce positively sloped sidewalls for imprinting purposes]] -->
  <!--  *[[Specific Process Knowledge/Etch/DRIE-Pegasus/slopedsidewalls|Etches that produce positively sloped sidewalls for imprinting purposes]] -->
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  <!-- *[[Specific Process Knowledge/Etch/DRIE-Pegasus/VeeryDeeep| Very deep etching]] -->
  <!-- *[[Specific Process Knowledge/Etch/DRIE-Pegasus/VeeryDeeep| Very deep etching]] -->


'''Advanced Processing - Henri Jansen style'''
=== Advanced Processing - Henri Jansen style ===
 
* [[Specific Process Knowledge/Etch/DRIE-Pegasus/Etch silicon nanostructures|Etch silicon nanostructures ]]
* [[Specific Process Knowledge/Etch/DRIE-Pegasus/Etch high aspect ratio silicon microstructures|Etch high aspect ratio silicon microstructures ]]
* [[Specific Process Knowledge/Etch/DRIE-Pegasus/Etch high aspect ratio silicon microstructures|Etch high aspect ratio silicon microstructures ]]
* [[Specific Process Knowledge/Etch/DRIE-Pegasus/Etch 3 dimensional silicon microstructures|Etch 3 dimensional silicon microstructures]]
* [[Specific Process Knowledge/Etch/DRIE-Pegasus/Etch 3 dimensional silicon microstructures|Etch 3 dimensional silicon microstructures]]
* [[Specific Process Knowledge/Etch/DRIE-Pegasus/Etch black silicon|Etch black silicon]]
* [[Specific Process Knowledge/Etch/DRIE-Pegasus/Etch black silicon|Etch black silicon]]
* [[/Using OES to monitor etch process|Using OES to monitor etch process]]
* [[Specific Process Knowledge/Etch/DRIE-Pegasus/Using OES to monitor etch process|Using OES to monitor etch process]]


'''Wafer bonding'''
=== Wafer bonding ===


To find information on how to bond wafers or chips to a carrier wafer, click [[Specific Process Knowledge/Etch/DryEtchProcessing/Bonding| here]].
To find information on how to bond wafers or chips to a carrier wafer, click [[Specific Process Knowledge/Etch/DryEtchProcessing/Bonding| here]].


'''Acceptance test'''
The instrument was opened for users in April 2010 when the acceptance test was signed. This was based on the performance of five standard recipes (A, B, C, D and SOI) that are further examined below. The acceptance test report is found [[Media:Pegasus_AcceptanceTest.pdf|here]].


'''Characterisation of etched trenches'''
'''Characterisation of etched trenches'''


Comparing differences in etched trenches requires a set of common parameters for each trench. Click [[Specific Process Knowledge/Etch/DRIE-Pegasus/TrenchCharacterisation|here]] to find more information about the parameters used on the DRIE-Pegasus process development.
Comparing differences in etched trenches requires a set of common parameters for each trench. Click [[Specific Process Knowledge/Etch/DRIE-Pegasus/TrenchCharacterisation|'''HERE''']] to find more information about the parameters used on the DRIE-Pegasus process development.
 
'''Material from SPTS'''
 
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/SPTSdocs|Hardware and process applications]]
 
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/FAQ|Miscellaneous information]]
 
'''Internal Danchip Process log'''
 
Process log at Danchip [http://labintra.danchip.dtu.dk/index.php/Main_Page/Process_Logs/jmli/Pegasus]
 
==Equipment performance and process related parameters==


{| border="2" cellspacing="0" cellpadding="2"


!colspan="2" border="none" style="background:silver; color:black;" align="center"|Equipment
'''Internal Nanolab Process log for Pegasus 1'''
|style="background:WhiteSmoke; color:black"|<b>DRIE-Pegasus</b>
|-
!style="background:silver; color:black;" align="center" width="80"|Purpose
|style="background:LightGrey; color:black"| Dry etch of
|style="background:WhiteSmoke; color:black"|
* Silicon
* Barc
|-
!style="background:silver; color:black" align="center" valign="center" rowspan="2"|Performance
|style="background:LightGrey; color:black"|Etch rates
|style="background:WhiteSmoke; color:black"|
* Standard processes A and B up to 15 µm/min depending on etch load and feature size
* Other processes: Any number from 200 nm/min to 10 µm/min
|-
|style="background:LightGrey; color:black"|Uniformity
|style="background:WhiteSmoke; color:black"|
* For standard processes better than 3 % across a 150 mm wafer.
|-
!style="background:silver; color:black" align="center" valign="center" rowspan="4"|Process parameter range
|style="background:LightGrey; color:black"|RF powers
|style="background:WhiteSmoke; color:black"|
* Coil Power 5 kW
* Platen power 300/500 W (HF/LF)
|-
|style="background:LightGrey; color:black"|Gas flows
|style="background:WhiteSmoke; color:black"|
* SF<sub>6</sub>: 0 to 1200 sccm
* O<sub>2</sub>: 0 to 200 sccm
* C<sub>4</sub>F<sub>8</sub>: 0 to 400 sccm
* Ar: 0 to 283 sccm
|-
|style="background:LightGrey; color:black"|Pressure and temperature
|style="background:WhiteSmoke; color:black"|
* Pressure range 4 to 250 mTorr
* Temperature range -20 to 30 degrees C
|-
|style="background:LightGrey; color:black"|Process options
|style="background:WhiteSmoke; color:black"|
* Bosch processes with etch and dep cycles possibly split into three individually controllable parts
* Parameter ramping during process steps
* SOI option to reduce notching at buried
|-


!style="background:silver; color:black" align="center" valign="center" rowspan="3"|Substrates
Process log at Nanolab [http://labintra.nanolab.dtu.dk/index.php/Main_Page/Process_Logs/jmli/Pegasus]
|style="background:LightGrey; color:black"|Batch size
|style="background:WhiteSmoke; color:black"|
*<nowiki>#</nowiki> small samples on carriers
*<nowiki>#</nowiki> 50 mm wafers: Bonded to carriers
*<nowiki>#</nowiki> 100 mm wafers: Up to 18 wafers in a batch process
*<nowiki>#</nowiki> 150 mm wafers: 1 wafer
|-
| style="background:LightGrey; color:black"|Allowed materials
|style="background:WhiteSmoke; color:black"|
* Silicon wafers
* Quartz wafers need a (semi)conducting layer for clamping
|-
| style="background:LightGrey; color:black"|Possible masking materials
|style="background:WhiteSmoke; color:black"|
* AZ photoresist
* zep resist
* DUV stepper resist (barc + krf)
* Oxides and nitrides
* Aluminium (only very mild processes such as process C and nanoetches)
|}
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