Jump to content

Specific Process Knowledge/Etch/III-V ICP/InP-InGaAsP-InGaAs: Difference between revisions

← Older edit
VisualWikitext
Bghe (talk | contribs)
DCH-Employees-701, NLAB-Employees-701, NLAB-LabmanagerAllUsers, Bureaucrats, Administrators
7,301 edits
Mmat (talk | contribs)
NLAB-Employees-701, NLAB-LabmanagerAllUsers, Administrators
1,954 edits
 
(25 intermediate revisions by 2 users not shown)
Line 1: Line 1:
'''Feedback to this page''': '''[mailto:labadviser@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.danchip.dtu.dk/index.php/Specific_Process_Knowledge/Etch/III-V_ICP/InP-InGaAsP-InGaAs click here]'''  
'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/III-V_ICP/InP-InGaAsP-InGaAs click here]'''  
<!-- Page reviewed 9/8-2022 jmli -->


=== InP etch with HBr chemistry===
 
 
 
== InP etch with HBr chemistry (2019)==
Work done by Aurimas Sakanas @Fotonik.dtu 2019. This work was done to obtain very low surface roughness.
Work done by Aurimas Sakanas @Fotonik.dtu 2019. This work was done to obtain very low surface roughness.
{| border="1" cellspacing="2" cellpadding="3"  
{| border="1" cellspacing="2" cellpadding="3"  
Line 48: Line 52:
|Selectivity (InP:HSQ)
|Selectivity (InP:HSQ)
|15:1 (2"), 20:1
|15:1 (2"), 20:1
|-
|Other tests
|Comparing this recipe with the Cl2/H2 recipe, click here: [[Media:HBr vs Cl2 InP etch comparison Aurimas.pptx]] ''(By Aurimas Sakana @photonic (nov 2019))
|-
|-
|}
|}
Line 68: Line 75:


</gallery>
</gallery>
=== InP etch with Cl2/H2 and a Si carrier wafer  [[Image:section under construction.jpg|70px]] ===
 
== InP etch with Cl2/H2 and a Si carrier wafer (2019) ==
''Work done by Berit Herstrøm @Nanolab spring 2019''
''Work done by Berit Herstrøm @Nanolab spring 2019''
<br>
This work was done with great inspiration from the following articles:
*'''Sidewall passivation assisted by a silicon coverplate during and HBr inductively coupled plasma etching of InP for photonic devices''' ''by S. Bouchoule, G. Patriarche, S. Guilet, L. Gatilova, L. Largeau, and P. Chabert'', Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 26, 666 (2008); doi: 10.1116/1.2898455
*'''Optimization of a inductively coupled plasma etching process adapted to nonthermalized InP wafers for the realization of deep ridge heterostructures''', ''by S. Guilet, S. Bouchoule, C. Jany, C. S. Corr, and P. Chabert'', Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 24, 2381 (2006); doi: 10.1116/1.2348728
*'''Investigation of InP etching mechanisms in a inductively coupled plasma by optical emission spectroscopy''', ''by L. Gatilova, S. Bouchoule, S. Guilet, and P. Chabert'', Journal of Vacuum Science & Technology A 27, 262 (2009); doi: 10.1116/1.3071950
{| border="1" cellspacing="2" cellpadding="3"  
{| border="1" cellspacing="2" cellpadding="3"  
|'''Recipe name'''
|'''Recipe name'''
Line 97: Line 114:
|Comment
|Comment
|Sample placed on a Si carrier
|Sample placed on a Si carrier
|-
|}
|}


Line 109: Line 127:
|
|
90<sup>o</sup> (on this sample)<br>
90<sup>o</sup> (on this sample)<br>
 
If you get a small tapered profile try lowering the platen power (to e.g. 100W), this will also decrease the etch rate
 
|-
|-
|Selectivity (InP:SiO2 (PECVD 500nm)
|Selectivity (InP:SiO2 (PECVD 500nm)
| approx.17:1
| approx.17:1
|-
|-
|Other tests made
|
*Comparing of this Cl2/H2 recipe with HBr recipe on e-beamed structures:[[Media:HBr vs Cl2 InP etch comparison Aurimas.pptx]] ''(By Aurimas Sakana @photonic (nov 2019))
''
*A few parameter variations on the recipe, [[/InP etch with Cl2-H2-Ar| see results on this page!]]
|-
|-
|}
|}
Line 125: Line 149:
</gallery>
</gallery>


*Comparing of this Cl2/H2 recipe with HBr recipe on e-beamed structures ''(By Aurimas Sakana @photonic (nov 2019))
== InP etch with Cl2/CH4/Ar 2013==
''
 
=== InP etch with Cl2/CH4/Ar 2013===
Work done by Matthew Haines in 2013 <br>
Work done by Matthew Haines in 2013 <br>
*[[Media:InP_Etch_Presentation_Final_Version-ky-bghe.pdf|InP Etch Presentation by Matthew Haines]]
*[[Media:InP_Etch_Presentation_Final_Version-ky-bghe.pdf|InP Etch Presentation by Matthew Haines]]


=== InP/InGaAsP/InGaAs etch 2011 ===
== InP/InGaAsP/InGaAs etch 2011 ==


Unselective etch for large sized features and small aspect ratios by David Larsson, DTU Photonics, 2011
Unselective etch for large sized features and small aspect ratios by David Larsson, DTU Photonics, 2011
Line 139: Line 160:
|'''Recipe'''
|'''Recipe'''
|'''InP Etch 1/InP Precond 1'''
|'''InP Etch 1/InP Precond 1'''
|?
|-  
|-  
|Cl<sub>2</sub> flow
|Cl<sub>2</sub> flow
|20 sccm
|20 sccm
|11 sccm
|-
|-
|N<sub>2</sub> flow
|N<sub>2</sub> flow
|40 sccm
|40 sccm
|20 sccm
|-
|-
|Ar flow
|Ar flow
|10 sccm
|10 sccm
|24 sccm
|-
|-
|Platen power
|Platen power
|100 W
|100 W
|120 W
|-
|-
|Coil power
|Coil power
|500 W
|500 W
|400 W
|-  
|-  
|Pressure
|Pressure
|2 mTorr
|2 mTorr
|2 mTorr
|-
|-
|Platen chiller  temperature
|Platen chiller  temperature
|180 <sup>o</sup>C
|180 <sup>o</sup>C
|180 <sup>o</sup>C
|-
|-
|Comment
|Comment
|Use SiO2 carrier (not Si) ''(Kabi/Bghe June 2018)''
|This is for large structures with samll aspect ratio <br> Use SiO2 carrier (not Si) ''(Kabi/Bghe June 2018)''  
|This is for high aspect ratio
|}
|}


Line 192: Line 222:


==InP etching June 2018==
==InP etching June 2018==
''Done by Kabi and Bghe @danchip''
''Done by Kabi and Bghe @nanolab''


===Sample pattern before etching===
===Sample pattern before etching===
Line 233: Line 263:


Image:S0_oxide_05.jpg|Sample S0: Top view of the oxide mask before etching. It is the TRAVKA50 mask, but it is clear that the CD reduction is about the 1-1.5 µm of the lines.
Image:S0_oxide_05.jpg|Sample S0: Top view of the oxide mask before etching. It is the TRAVKA50 mask, but it is clear that the CD reduction is about the 1-1.5 µm of the lines.
Image:none
Image:S4_06.jpg|Sample S4: Profile view. The recipe InP etch has been used. <br> The sample has been run on a SiO2 carrier wafer. <br> There is not much CD change compared to the oxide mask before the etch. <br> It seems like the SiO2 mask is gone and the sidewall angle from the mask has been transferred into the sample. <br> The sidewall profile is quit vertical in the lower part. <br> Etch time 15 min <br> Etch depth in large open areas: 9.19µm
Image:S4_06.jpg|Sample S4: Profile view. The recipe InP etch has been used. <br> The sample has been run on a SiO2 carrier wafer. <br> There is not much CD change compared to the oxide mask before the etch. <br> It seems like the SiO2 mask is gone and the sidewall angle from the mask has been transferred into the sample. <br> The sidewall profile is quit vertical in the lower part. <br> Etch time 15 min <br> Etch depth in large open areas: 9.19µm
Image:S5_05.jpg|Sample S5: Profile view. The recipe InP etch has been used but with modified Cl2 and N2 flows: N2=30 sccm Cl2=30 sccm. <br> The sample has been run on a SiO2 carrier wafer. <br> There is not much CD change compared to the oxide mask before the etch. <br> It seems like the SiO2 mask is gone. <br> The sidewall profile is overcutting probably due to too little passivation. <br> Etch time 10 min <br> Etch depth in large open areas: 11.82µm
Image:S5_05.jpg|Sample S5: Profile view. The recipe InP etch has been used but with modified Cl2 and N2 flows: N2=30 sccm Cl2=30 sccm. <br> The sample has been run on a SiO2 carrier wafer. <br> There is not much CD change compared to the oxide mask before the etch. <br> It seems like the SiO2 mask is gone. <br> The sidewall profile is overcutting probably due to too little passivation. <br> Etch time 10 min <br> Etch depth in large open areas: 11.82µm
Image:S4_30dg_2_05.jpg|Sample S4: The sidewall roughness on the sample S4 is quit high
Image:S4_30dg_2_05.jpg|Sample S4: The sidewall roughness on the sample S4 is quite high
Image:S5_30dg_01.jpg|Sample S5: The sidewall roughness on the sample S5 is quit low.  
Image:S5_30dg_01.jpg|Sample S5: The sidewall roughness on the sample S5 is quite low.  


</gallery>
</gallery>
Retrieved from "https://labadviser.nanolab.dtu.dk//index.php?title=Specific_Process_Knowledge/Etch/III-V_ICP/InP-InGaAsP-InGaAs"