Specific Process Knowledge/Thin film deposition/Furnace LPCVD TEOS: Difference between revisions

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<i> Unless otherwise stated, this page is written by <b>DTU Nanolab internal</b></i>


[[Category: Equipment|Thin film LPCVD TEOS]]
[[Category: Equipment|Thin film LPCVD TEOS]]
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[[Category: Furnaces|LPCVD TEOS]]
[[Category: Furnaces|LPCVD TEOS]]


==LPCVD TEOS oxide==
==B3 LPCVD TEOS furnace==
[[Image:160904_danchip_4538.jpg|300x300px|thumb|B3 Furnace LPCVD TEOS. Positioned in cleanroom B-1]]
[[Image:160904_danchip_4538.jpg|300x300px|thumb|B3 LPCVD TEOS furnace. Positioned in cleanroom B-1]]
 
DTU Nanolab has one LPCVD (Low Pressure Chemical Vapor Deposition) TEOS furnace, in LabManager "Furnace: LPCVD TEOS (B3)".


DTU Nanolab has one LPCVD (Low Pressure Chemical Vapor Deposition) TEOS furnace. The furnace is a Tempress horizontal furnace (installed in 1995). The process is a batch process, where TEOS oxide can be deposited on up to 15 4" wafers at a time.  
The furnace is a Tempress horizontal furnace (installed in 1995). The process is a batch process, where TEOS oxide can be deposited on up to 15 4" wafers at a time.  


TEOS is tetraethoxysilane, and TEOS oxide is a silicon dioxide based on this reactive chemical that during deposition condenses on the sample surface. The deposition takes place at a temperature of 712-720 <sup>o</sup>C (there is a small temperature gradient over the furnace tube).  
TEOS is tetraethoxysilane, and TEOS oxide is a silicon dioxide based on this reactive chemical that during deposition condenses on the sample surface. The deposition takes place at a temperature of 712-720 <sup>o</sup>C (there is a small temperature gradient over the furnace tube).  
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It is possible to anneal TEOS oxide layers to increase the density and thus improve the electrical properties as well as the chemical resistance. The electrical characteristics may also be improved by the addition of O<sub>2</sub> during the deposition process.
It is possible to anneal TEOS oxide layers to increase the density and thus improve the electrical properties as well as the chemical resistance. The electrical characteristics may also be improved by the addition of O<sub>2</sub> during the deposition process.


LPCVD TEOS oxide has an excellent step coverage and is very good for trench filling, however very small nanometer trenched and/or very deep trenches will be challenging to fill. The film thickness is very uniform over each wafer.  
LPCVD TEOS oxide has an excellent step coverage and is very good for trench filling, however very small nanometer trenched and/or very deep trenches will be challenging to fill. The film thickness over the wafers is very uniform.


More information about the TEOS oxide deposition process can be found here:
More information about the TEOS oxide deposition process can be found here:
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*[https://labmanager.dtu.dk/view_binary.php?class=MiscDocument&id=19&name=Furnace+computer+manual+April+2024.pdf  See LabManager (requires a login)]
*[https://labmanager.dtu.dk/view_binary.php?class=MiscDocument&id=19&name=Furnace+computer+manual+April+2024.pdf  See LabManager (requires a login)]


==Process Knowledge==
==Process knowledge==
Please take a look at the process side for deposition of TEOS oxide:
Please take a look at the process side for deposition of TEOS oxide:


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|style="background:LightGrey; color:black"|
|style="background:LightGrey; color:black"|
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
Deposition of TEOS - Silicon dioxide based on tetraethoxysilane
Deposition of TEOS oxide
|-
|-
!style="background:silver; color:black" align="center" valign="center" rowspan="3"|Performance
!style="background:silver; color:black" align="center" valign="center" rowspan="3"|Performance
|style="background:LightGrey; color:black"|Film thickness
|style="background:LightGrey; color:black"|Film thickness
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*0 nm - 2000 nm
*Up to 3000 nm
|-
|-
|style="background:LightGrey; color:black"|Step coverage
|style="background:LightGrey; color:black"|Step coverage
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*Good
*Very good
|-
|-
|style="background:LightGrey; color:black"|Film quality
|style="background:LightGrey; color:black"|Film quality
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|-
|-
!style="background:silver; color:black" align="center" valign="center" rowspan="3"|Process parameter range
!style="background:silver; color:black" align="center" valign="center" rowspan="3"|Process parameter range
|style="background:LightGrey; color:black"|Process Temperature
|style="background:LightGrey; color:black"|Process temperature
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*712-720 <sup>o</sup>C
*712 - 720 <sup>o</sup>C
|-
|-
|style="background:LightGrey; color:black"|Process pressure
|style="background:LightGrey; color:black"|Process pressure
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*190 mTorr
*175 mTorr
|-
|-
|style="background:LightGrey; color:black"|Gas flows
|style="background:LightGrey; color:black"|Gas flows
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*TEOS: 50 sccm
*TEOS (tetraethoxysilane): ~50 sccm. <i>The exact flow is not know - the setpoint is much lower than 50 sccm, because the MFC is not calibrated for TEOS</i>
*O<sub>2</sub>: 0 sccm
*O<sub>2</sub>: 0 sccm
|-
|-
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|style="background:LightGrey; color:black"|Batch size
|style="background:LightGrey; color:black"|Batch size
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*1-15 4" wafers per run
*1-15 4" wafers per run (including a test wafer)
*Deposition on both sides of the substrate
*Deposition on both sides of the wafers
|-
|-
| style="background:LightGrey; color:black"|Substrate material allowed
| style="background:LightGrey; color:black"|Substrate materials allowed
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*Silicon wafers (only clean wafers and RCA cleaned)
*Silicon and fused silica/quartz wafers. <i>New wafers supplied by Nanolab can to go directly into the furnace</i>
**with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned)
*Wafers from the A stack, B stack and E stack furnaces. <i> The wafers have to go directly into the furnace </i>
**from furnaces in stack A or B in cleanroom 2
*Processed wafers (only allowed materials - see the cross contamination information in LabManager). <i> The wafers have to be RCA cleaned </i>
*Quartz wafers (RCA cleaned)
 
*Silicon carbide sample(RCA cleaned)
Note:
*RCA cleaned wafers can be stored in an RCA transfer box.
*Wafers must NOT have been exposed to metal prior to processing, and they must not have been stored in dirty boxes (e.g. boxed that might have contained wafers with metal).
|-  
|-  
|}
|}


== Rules for storage and RCA cleaning of wafers to the B3 furnace ==
== Rules for storage and RCA cleaning of wafers to the B3 furnace ==


*[[Specific_Process_Knowledge/Thermal_Process/Storage_and_cleaning_of_wafer_to_the_A,_B,_C_and_E_stack_furnaces|Storage and cleaning of wafer to the B3 furnace]]
*[[Specific_Process_Knowledge/Thermal_Process/Storage_and_cleaning_of_wafer_to_the_A,_B,_C_and_E_stack_furnaces|Storage and cleaning of wafer to the B3 furnace]]

Latest revision as of 16:14, 6 March 2025

The contents on this page, including all images and pictures, was created by DTU Nanolab staff unless otherwise stated.

Feedback to this page: click here

B3 LPCVD TEOS furnace

B3 LPCVD TEOS furnace. Positioned in cleanroom B-1

DTU Nanolab has one LPCVD (Low Pressure Chemical Vapor Deposition) TEOS furnace, in LabManager "Furnace: LPCVD TEOS (B3)".

The furnace is a Tempress horizontal furnace (installed in 1995). The process is a batch process, where TEOS oxide can be deposited on up to 15 4" wafers at a time.

TEOS is tetraethoxysilane, and TEOS oxide is a silicon dioxide based on this reactive chemical that during deposition condenses on the sample surface. The deposition takes place at a temperature of 712-720 oC (there is a small temperature gradient over the furnace tube).

It is possible to anneal TEOS oxide layers to increase the density and thus improve the electrical properties as well as the chemical resistance. The electrical characteristics may also be improved by the addition of O2 during the deposition process.

LPCVD TEOS oxide has an excellent step coverage and is very good for trench filling, however very small nanometer trenched and/or very deep trenches will be challenging to fill. The film thickness over the wafers is very uniform.

More information about the TEOS oxide deposition process can be found here:

Deposition of TEOS oxide using LPCVD


The user manual(s), quality control procedure(s) and results, technical information and contact information can be found in LabManager:

LPCVD TEOS furnace

Furnace computer manual

No quality control is done for the LPCVD TEOS oxide furnace

Manual for the furnace computer to the A, B, C and E stack furnaces

The A, B, C and E stack furnaces can be controlled either from a touch screen by each furnace or from a furnace computer.

The user manual for the furnace computer can be found here:

Process knowledge

Please take a look at the process side for deposition of TEOS oxide:

Deposition of TEOS using LPCVD

Overview of the performance of the LPCVD TEOS furnace and some process related parameters

Purpose

Deposition of TEOS oxide

Performance Film thickness
  • Up to 3000 nm
Step coverage
  • Very good
Film quality
  • Dense film
  • Few defects
Process parameter range Process temperature
  • 712 - 720 oC
Process pressure
  • 175 mTorr
Gas flows
  • TEOS (tetraethoxysilane): ~50 sccm. The exact flow is not know - the setpoint is much lower than 50 sccm, because the MFC is not calibrated for TEOS
  • O2: 0 sccm
Substrates Batch size
  • 1-15 4" wafers per run (including a test wafer)
  • Deposition on both sides of the wafers
Substrate materials allowed
  • Silicon and fused silica/quartz wafers. New wafers supplied by Nanolab can to go directly into the furnace
  • Wafers from the A stack, B stack and E stack furnaces. The wafers have to go directly into the furnace
  • Processed wafers (only allowed materials - see the cross contamination information in LabManager). The wafers have to be RCA cleaned

Note:

  • RCA cleaned wafers can be stored in an RCA transfer box.
  • Wafers must NOT have been exposed to metal prior to processing, and they must not have been stored in dirty boxes (e.g. boxed that might have contained wafers with metal).

Rules for storage and RCA cleaning of wafers to the B3 furnace