Specific Process Knowledge/Etch/ICP Metal Etcher/Chromium: Difference between revisions
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The Chromium etch was carried out on the following substrate stack: | The Chromium etch was carried out on the following substrate stack: | ||
2" Si wafer with Cr laying in a 6" Si wafer with a 4" recess. The area outside the recess was covered by AZ resist. | 2" Si wafer with Cr laying in a 6" Si wafer with a 4" recess. The area outside the recess was covered by AZ resist. | ||
The work was carried out | The work was carried out by Erol Zekovic @Nanotech and BGHE@nanolab | ||
* [[/End point|Cr etch - when to stop using end point detecting]] | |||
{| border="2" cellpadding="2" cellspacing="1" style="text-align:center;" | {| border="2" cellpadding="2" cellspacing="1" style="text-align:center;" | ||
|+ '''Cr etch''' | |+ '''Cr etch''' | ||
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| Was masked by capton tape | | Was masked by capton tape | ||
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<gallery caption="Etching lines in 100nm Cr with the Cr etch for 3:30 min with 500 nm DUV resist on a 22mmx22mm piece ''BGHE@Nanolab Jan 2023''" perrow="5" widths="400px" heights="300px"> | |||
File:s040321_02.jpg | |||
File:s040321_05.jpg | |||
File:s040321_08.jpg | |||
File:s040321_11.jpg | |||
File:s040321_12.jpg | |||
File:s040321_14.jpg | |||
</gallery> | |||
<gallery caption="Etching lines in 100nm Cr with the Cr etch for 3 min with 300 nm DUV resist ''BGHE@Nanolab Feb 2022''" perrow="5" widths="400px" heights="300px"> | <gallery caption="Etching lines in 100nm Cr with the Cr etch for 3 min with 300 nm DUV resist ''BGHE@Nanolab Feb 2022''" perrow="5" widths="400px" heights="300px"> | ||