Specific Process Knowledge/Lithography/EBeamLithography/FilePreparation: Difference between revisions
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For pattern exposure on the JEOL 9500 tool the pattern must be stored in JEOLs own proprietary JEOL52v3.0 format, also known as V30. At DTU Nanolab we use Beamer to generate the V30 file from the original design file. We recommend using GDS as the original file format although Beamer can read multiple formats. In addition to the a pattern file exposure requires a Schedule file (SDF) and a Jobdeck file (JDF). These are text files where the user defines exposure conditions. Before pattern writing these three files (V30, SDF and JDF) are compiled into a final magazine file (MGN) which fully defines the exposure job. | For pattern exposure on the JEOL 9500 tool the pattern must be stored in JEOLs own proprietary JEOL52v3.0 format, also known as V30. At DTU Nanolab we use Beamer to generate the V30 file from the original design file. We recommend using GDS as the original file format although Beamer can read multiple formats. In addition to the a pattern file exposure requires a Schedule file (SDF) and a Jobdeck file (JDF). These are text files where the user defines exposure conditions. Before pattern writing these three files (V30, SDF and JDF) are compiled into a final magazine file (MGN) which fully defines the exposure job. | ||
== Conversion from GDS to V30 in Beamer == | |||
Beamer has a lot of different modules and can be used to manipulate a design considerably. In this section we will only look at how to import a design file and export it to V30. | |||
Beamer uses a node based workflow and each task is defined by a node with its own set of parameter. For this simple example we will only use the "Import" and "Export" nodes. | |||
== Basic SDF conten == | |||
== Basic JDF content == | |||
If the layout is asymmetric, the conversion might result in an offset of the final layout onto the wafer. It is therefore recommended to symmetrise the layout, e.g. by inserting small structures in the corners of a rectangle that covers the layout. | If the layout is asymmetric, the conversion might result in an offset of the final layout onto the wafer. It is therefore recommended to symmetrise the layout, e.g. by inserting small structures in the corners of a rectangle that covers the layout. | ||
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DIRE01 INITIAL: PDEFBE, SUBDEFBE, CURRENT | DIRE01 INITIAL: PDEFBE, SUBDEFBE, CURRENT | ||
CYCLIC: CURRNT (every 5 minutes without interupting the writing of a field) | CYCLIC: CURRNT (every 5 minutes without interupting the writing of a field) | ||
</pre> | |||
The full list of calibration [[Specific_Process_Knowledge/Lithography/EBeamLithography/FilePreparation/Pathlist|paths are available here.]] | |||
== Alignment and global mark detection == | == Alignment and global mark detection == | ||
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[[File:markorientation.jpg|300px]] | [[File:markorientation.jpg|300px]] | ||
note 2: Always add | note 2: Always add 5% to the current in this command to make sure you work well below 200 MHz and thus will not be affected if the current fluctuates above the base current. | ||
== Dose variation == | == Dose variation == | ||