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| <!--Checked for updates on 30/7-2018 - ok/jmli -->
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| '''Feedback to this page:
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| [mailto:plasma@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.danchip.dtu.dk/index.php/Specific_Process_Knowledge/Etch/DRIE-Pegasus/FAQ/Matching click here]'''
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| ; Question 1
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| :Last Friday I ran the first nanoetches with the recipe below - with limited success however. I was short on time so I couldn't investigate it further but for some reason the coil power would rise to some 1500 W in the first few seconds of the etch and og out of tolerance. I tried switching to forward power, no success. I copied a switched recipe and adjusted all the parameters that I know to change and switched to continuous tolerance recipe. What about matching, wouldn't it be good idea to try and run the process manually (ramping up RF powers and allowing the matching network to stabilize and setting the load/tune parameters as starting points?) and I don't need to strike the plasma...?
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| ; Answer 1
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| :It is odd that the power delivery went up to 1500W when the demand was 800W. It sounds like the matching needs to be looked at more closely. Careful set up of the starting positions will be needed; these will likely be different to what has worked before in any other recipe as the conditions for this process are quite different.
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| :It will be worth doing a trial run on a PR-coated or oxide wafer where a strike pressure of 20mT is allowed just to get the plasma struck, then record the load and tune values when the pressure gets to the desired 4mT and is running stable. The load and tune start points should then be set to values ~5% away from the "sweet spot"; when the RF first comes on the transient in the impedance forces the matching unit to search - we want the unit to search towards the sweet spot positions and not away from them - if the start point is set to the best vale then it will likely never match properly as the caps will drive away from these positions as soon as the power comes through.
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| :There are two methods of achieving good matching:
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| :1. Start points set to 5% below and 5% above the sweet spot on the Load and Tune respectively OR
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| :2. The Load set to start in the sweet spot position and Tune set 5% below 4mT is a difficult pressure to strike at so it may be necessary to use the strike pressure anyway; only 3s of plasma in 10-20mT strike pressure range should havel ittle-to-no effect on the process result.
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| ; Question 2
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| :I have tried many times now and I can't find a stable, repeatable process. I would like you to comment on the following facts/observations: I try to find a stable process on a 4" si wafer coated with AZ PR with 80 % exposed to plasma. The actual wafers are 2" Si wafers with some 100 nm ZEP resist and only very small nm-sized areas in the center and lying on 4" dummy wafer with 2" reces.
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| ; Answer 2
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| :This is an unusual mix. The set up wafer sounds fine - standard 100mm wafer with AZ PR coating. The 2" wafer on 4" dummy is unusual in Pegasus (most Pegasus tools are at 150-200mm), I have completed many process runs on mounted-wafer pieces using coogrease or crystalbond which would likely mimic your set up. What is unusual is the "dummy wafer with 2" recess" - I am not sure what this is. Either way, this should have no effect on the coil matching.
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| ; Question 3
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| :I don't know why the coil power shoots up (sometimes above 2000 W) in the very first seconds of the etch. Adding a 15 second strike @ 15 mtorr, playing around with coil matching parameters (as suggested by you below), using load or forward coil power or introducing 15 seconds gas stabilizations do not seem to make much difference.
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| ;Answer 3
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| :The two datalogs you sent do not show any issue with reflected coil power in the first few seconds of processing. There is no large reflected power spike and coil matching unit performance looks stable. 15s gas stabilisation should ALWAYS be run - the most important part of the stabilisation is the homing of the matching unit to ensure that the unit "knows" where the capacitors are at and also there is a physical HF/LF switch in the platen matching which only changes during the stabilisation...i.e. a HF process run with no stabilisation after a LF process would have the platen matching switch still set to LF. Without stabilisation, there are likely to be matching issues on the coil and possibly on the platen depending on previous process run.
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| :It is expected to see a reflected power spike at the start of the process as the plasma is being struck; provided that this spike comes down very quickly there is usually no issue. Also, it is important that the matching start points are set ~5% away from the "sweet spot" to ensure that the matching is repeatable run-to-run during the transient phase as the plasma strikes; if the matching is not set up well, then it is a matter of luck.....some runs will strike well, others will not.
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| ;Question 4
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| : Would it be a good idea to run a conditioning run before the wafers and after TDESC cleans. I have tried to make a conditioning recipe with a ramping step where the coil power is ramped from 300 to 800 W in 30 seconds in order for the matching unit to find the sweet spot more easily before a 'non-ramped' step.
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| ; Answer 4
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| : Provided usual inter-wafer (waferless) clean protocol is followed, there should be no need for specific conditioning runs. It may be worth running a few minutes of the desired process when switching from a very different process window but there should be little/no difference provided a 3minute interwafer clean is run immediately before any process run. To clarify:
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| : 1. In "development mode" (only few-several runs per day) 3minute clean before the process run is needed.
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| : 2. In "production mode" (continuous running of batch processes), 3minute clean at the very start followed by interwafer clean (time of interwafer clean should follow a rough rule of thumb of ~3s clean/minute of actual processing + ~10% if process time is longer than a a few minutes, otherwise, for very short processes a batch clean of ~30minutes to 1hr depending on duration of batch process).
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| ; Question 5
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| : A colleague who is working hard to find the right Cr etch on our ICP metal etcher has just been informed that due to the usage of the '10% range' option on the platen power her processes have been running with 10 times as much platen power as intended. In my experiments so far I have seen that the 100 nm of ZEP resist is gone after 30 seconds of processing...
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| ; Answer 5
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| : I'm not sure of the details on the metal etcher. On the Pegasus, selecting 10% range will limit the range to 30W, selecting "full" will allow up to 300W. You are running 50W with this process - the range should be set to full. If running <30W, then setting full range will not deliver 10x more power than requested, just that the control of fwd power will not be as accurate as if 10% range is selected (i.e. 0-5V = 0-30W in 10% range, 0-5V = 0-300W in full range). I think that on the metal etcher there is an issue due to the different platen generator. It is worth double-checking the generator display on the Pegasus when running low power and 10% range selected as this is a combination not very often used.
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| : 100nm of ZEP resist is not much and it is feasible to think that this is stripping off in 30s of process time. ZEP resist will show a much lower selectivity than standard resist. The conditions are going to be quite hard on the mask - low pressure and relatively high platen power. Use of ZEP resist and the process conditions you are running is very rare in the Pegasus - it is difficult to say what you should expect to see.
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| : How is the 2" wafer bonded to the carrier and what is the carrier? If thermal bonding is not good such that the cooling is lost or not efficient, then there will be lack of deposition on the mounted wafer resulting in low selectivity.
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| ; Question 6
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| : I have attached the recipes that I am using - can you find any bad parameters?
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| ; Answer 6
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| : Aside from the lack of stabilisation in some of the recipes and use of 10% range in platen power (which will probably limit forward power to 30W when demand is 50W), I cannot see anything wrong with the processes.
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| Source: Kerry Roberts, SPTS
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