View source for LabAdviser/Technology Research/Nanoscale Dry Etching - Technology Development and Applications

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=Technology Development of 3D Silicon Plasma Etching process for Novel Devices and Applications=
*'''Project type:''' Ph.d. project
*'''Project responsible:''' Ph.d. student Bingdong Chang
*'''Supervisors:'''
*'''Partners involved:''' DTU Danchip

==Project Description==

Plasma processes are important for silicon-based micro electromechanical systems (MEMS) with critical dimensions around a few microns. With the lithographic tools pushing the limits further down, also the dimensions of MEMS devices are rapidly decreasing and commercial nano electromechanical systems (NEMS) are underway. Emerging applications include NEMS resonators and sensors for physical and bio-chemical sensing down to the molecular level both because of the much reduced mass, nanowires for novel transistors and photovoltaics increasingly exploring quantum effects starting at the sub-50nm level, nanostructures for photonics (around the wavelength of the guided photons) and next generation storage (10nm and below), black silicon for large area catalysed reaction chambers and photovoltaics, through wafer vias for packaging applications, and nano imprint lithography (NIL) masters. Furthermore, instead of silicon, diamond is increasingly important as a structural material because of its remarkable properties such as electrical conductivity and hardness.

Typically all these devices have customized process flows but synergies can be found as most are produced using a 2.5D approach comprising sequential deposition, lithography and etch steps. The majority, such as accelerometers and gyroscopes, are based on sub-100 micron depth features with piezo-resistive transduction or submicron gap capacitive sensing. Trends are towards higher aspect ratio etches (depth/width>30) and small footprint devices for enhanced performance. Increasingly, large cavities (10-100 microns in width) are being etched for subsequent chip or wafer scale packaging and sensor structures may comprise multi-wafer stacks with one or more having through wafer etches (200-800 microns deep). High speed etching with excellent profiles control to facilitate e.g. copper feedthroughs is indispensable for such applications. For NIL applications, it is essential that the mold releases cleanly and a smooth sidewall without any negative profile that would prevent release.

Although widely utilized and largely understood, silicon etch processes fail to reproduce at the nanoscale. Transport effects ‘down the etched cavity’ limit rate and selectivity while aspect ratios, profile and passivation control are more challenging. For example, aspect ratios beyond 30 are rarely utilized and fluctuations in the results are common. So, at the nanoscale, etching becomes more difficult. Basically, two types of etching techniques can be distinguished; the continuous (or mixed) process and the alternating (or pulsed/Bosch) process. The continuous process generally has smooth sidewalls and low undercut and it is the standard technique in mainstream nano-electronic chip fabrication. However, at room temperature the mixed gas process, results in a low rate 

selectivity and aspect ratio capability – as such it is limited to shallow features. The alternating etch process is probably the most popular technique in MEMS production facilities today. It uses a repeating sequence of plasma enhanced deposition to passivate silicon features, a physical etch for directional removal of this layer at the base of the features, and an isotropic etch for silicon removal at the cleared surfaces. However, it is not well suited to the nanoscale due to finite sidewall scallop size and undercut unless rate and selectivity are severely compromised. Typically it is not applied below 500nm trench feature sizes – although 100nm features have been demonstrated.

The major part of this project will be related to experimental work in the cleanroom facility at DTU Danchip. It is the quest to develop a fundamental understanding of the special challenges involved in dry etching at the nanoscale including the physics and chemistry involved in the processing. The aim is to establish a generic knowledge platform for the nanoscale dry etching for future applications. An important part of the project will be to demonstrate the ability in some state-of-the-art and novel NEMS applications mentioned above, especially to design and fabricate photonic crystals and Casimir oscillators. 

The former, photonic crystals, or photonic bandgap (PBG) structures, have spatially periodical regions of different dielectric constants, and its repeating unit size is normally comparable to the wavelength of light. Because its unique optical band structure provides possibility to control and manipulate light, many applications in optical communication have been studied widely, e.g. waveguides, and high resolution filters. Just as in solid state physics, by carefully introducing defects in photonic crystals, it is possible to trap light, even to create different energy levels. Another intriguing adaptation of PBG idea in phonon engineering is phononic crystals. Just as electrons and photons, by designing fine structures on nanoscale, phonons of certain modes will be confined, thus giving rise to special thermal performance of the material. It has been proposed that this reduction of thermal conductivity can be used to conserve thermal energy and convert to electricity with a higher efficiency. However, to fabricate phononic crystals, especially in 3D, requires technological proficiencies in micro- and nanofabrication.

The later, Casimir oscillators, is based on the Casimir effect, which is an quantum effect that is deeply related to various fields from nanoscale to Hubble-scale, e.g. gecko’s feet, quantum levitation, Hawking radiation, etc. It has attracted enormous research interest in both theory and experiment. It has also been claimed that, the Casimir effect can be the cause of failure in NEMS, i.e. permanent stiction of nanodevices with substrates. The Casimir force starts to play a role in the 100nm range, and is extremely sensitive to the geometry. A classic example is the Casimir force between two parallel plates with perfect conductivity (with vacuum in between). This specific boundary condition will give an attraction force that is proportional to S/d^4 (S is the surface area of the plate, and d is the distance between the two plates). It can be imagined that, if two plates with large area are aligned with a short distance in between, the Casimir force can easily be detected and even utilized. However, to manufacture two plates with large area and smooth surfaces, and to align them perfectly in a parallel position, can be a huge test for current nanofabrication technologies, especially for dry etching, which will be a necessary stage in the manufacturing. Previously, to avoid this problem, a completely different geometrical design based on a sphere and a plate has been tested. However, this design will give a force proportional to  R/d^3 (R is the radius of the sphere and d is the distance between sphere and plate), which is much smaller than the force between two plates and more difficult to detect. Some researchers claim that they have manufactured Casimir oscillator based on sphere-plate geometry. However, to make a Casimir oscillator with a higher S/N ratio, and to study the effect of medium (which can lead to astonishing Casimir repulsion force), plate-plate geometry is a better choice, and thus will be my focus of research in the project.

For this, a modern e-beam lithography tool will be utilized to define the NEMS structure down to 10nm critical dimension on top of a silicon on insulator (SOI) wafer. Subsequently, the pattern is transferred into the silicon layer using a modern high-density plasma tool. Finally, for certain applications the NEMS structure has to be released using isotropic undercutting of the oxide. If time permits the processing will be extended to diamond and diamond on insulator films.