View source for Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Silicide/V3Si RF-DC Co-Sputtering in Cluster Lesker PC3

<i>This page is written by <b>Evgeniy Shkondin @ DTU Nanolab</b> if nothing else is stated.<br>
All images and data on this page belong to <b>DTU Nanolab</b>.<br>
The exploratory deposition and characterization described below were performed in <b>2025</b>.<br></i>

=Exploratory V-Si RF-DC co-sputtering in Cluster Lesker PC3=

This page documents an early, non-systematic attempt to deposit vanadium silicide by simultaneous RF sputtering of a 4-inch Si target and DC sputtering of a 3-inch V target in the <i>Cluster Lesker PC3</i> chamber. Two otherwise nominally identical depositions were compared: one without RF substrate bias and one with 30 W RF substrate bias.

The experiment gave a striking result. In the measured 30–80&deg; GiXRD range, the unbiased sample showed only reflections assigned to cubic A15 V<sub>3</sub>Si, whereas the sample deposited with 30 W RF substrate bias showed only reflections assigned to hexagonal C40 VSi<sub>2</sub>. The two samples also had very different surface morphologies and sheet resistances.

This PC3 experiment is separate from the later, systematic V<sub>3</sub>Si process-development study performed in PC1.


==Substrate and deposition conditions==

* Substrate: 150 mm Si(100) wafer
* Surface preparation: native SiO<sub>2</sub> removed by HF immediately before deposition
* Si source: 4-inch Si target, RF sputtering
* V source: 3-inch V target, DC sputtering
* Working pressure: 3 mTorr
* Deposition temperature: 600 &deg;C
* Deposition time: 1200 s
* Substrate-bias comparison: no RF bias versus 30 W RF bias
* Recorded DC substrate-bias voltage at 30 W RF bias: 69 V

{| border="2" cellspacing="2" cellpadding="5" class="wikitable" style="text-align:center;"
|+'''PC3 V-Si co-sputtering conditions'''
|-
! Condition
! Si target
! Si power
! Displayed Si voltage
! V target
! V power
! Displayed V voltage
! Pressure
! RF substrate power
! Substrate DC bias
! Temperature
! Time
|-
| No substrate bias
| 4-inch Si
| 120 W RF
| 100 V
| 3-inch V
| 100 W DC
| 322 V
| 3 mTorr
| 0 W
| Not applied
| <b>600 &deg;C</b>
| 1200 s
|-
| 30 W RF substrate bias
| 4-inch Si
| 120 W RF
| 110 V
| 3-inch V
| 100 W DC
| 309 V
| 3 mTorr
| 30 W
| 69 V
| <b>600 &deg;C</b>
| 1200 s
|}

Although the applied target powers were unchanged, the displayed Si and V discharge voltages changed when the substrate RF bias was enabled. This shows that the plasma impedance/coupling was not identical in the two runs. Consequently, the elemental rates measured in separate calibration depositions should be treated as nominal flux estimates rather than exact in-situ co-deposition rates.

=Power calibration and estimated V:Si atomic-arrival ratio=

The individual elemental deposition rates measured at 3 mTorr were:

{| border="2" cellspacing="2" cellpadding="5" class="wikitable" style="text-align:center;"
|+'''Individual elemental-rate calibration'''
|-
! Element
! Target size
! Mode
! Power
! Pressure
! Pure-element thickness rate
! Density used
! Molar mass used
|-
| Si
| 4 inch
| RF
| 120 W
| 3 mTorr
| 0.024 nm/s
| 2.329 g/cm<sup>3</sup>
| 28.0855 g/mol
|-
| V
| 3 inch
| DC
| 100 W
| 3 mTorr
| 0.0700 nm/s
| 6.11 g/cm<sup>3</sup>
| 50.9415 g/mol
|}

The thickness-rate ratio was therefore:

<math>
\frac{r_V}{r_{Si}}=\frac{0.0700}{0.024}=2.92
</math>

This number cannot be compared directly with the 3:1 atomic stoichiometry of V<sub>3</sub>Si. For an elemental rate calibration, the atomic arrival rate is proportional to:

<math>
\Phi_i \propto \frac{\rho_i r_i}{M_i}
</math>

where <math>\rho_i</math> is the elemental density, <math>r_i</math> is the pure-element thickness rate, and <math>M_i</math> is the molar mass. The nominal target-derived atomic-arrival ratio is consequently:

<math>
\frac{\Phi_V}{\Phi_{Si}}=
\frac{\rho_V r_V/M_V}{\rho_{Si}r_{Si}/M_{Si}}
=4.22
</math>

Thus, the flux supplied by the two targets was nominally about 80.8 at.% V and 19.2 at.% Si, corresponding to V<sub>4.22</sub>Si rather than V<sub>3</sub>Si. The pure-element thickness-rate ratio required for an atomic V:Si ratio of 3 is approximately:

<math>
\left(\frac{r_V}{r_{Si}}\right)_{V_3Si}
=3\frac{M_V/\rho_V}{M_{Si}/\rho_{Si}}
=2.07
</math>

The calibrated target flux was therefore substantially more V-rich than the ideal V<sub>3</sub>Si value. The formation of V<sub>3</sub>Si in the unbiased sample cannot be explained by the target flux alone; Si supplied by the oxide-stripped Si wafer must be considered.

==Simple target/substrate mass balance==

Using the calibrated rates and 1200 s deposition time, and assuming for the moment that all deposited V was retained:

* formation of V<sub>3</sub>Si requires approximately <b>11.7 nm of substrate-equivalent Si</b> in addition to the Si supplied by the target;
* the corresponding full-retention V<sub>3</sub>Si layer thickness is approximately <b>105 nm</b> using a bulk V<sub>3</sub>Si density of 5.77 g/cm<sup>3</sup>;
* the measured no-bias XRR thickness was 94.046 nm, about 89% of this simple mass-balance value.

The agreement is reasonable for separately calibrated rates, compound formation, a simplified XRR model, and a process performed at 600 &deg;C. It supports substrate participation but is not an independent composition measurement.

If all calibrated V instead formed VSi<sub>2</sub>, the limiting mass balance would require approximately <b>214 nm of additional substrate-equivalent Si</b> and would produce roughly <b>244 nm of VSi<sub>2</sub></b> using a density of 4.42 g/cm<sup>3</sup>. These are not measured values for the biased sample. They illustrate that formation of VSi<sub>2</sub> throughout the deposited material would require extensive Si uptake from the wafer, a change in retained V flux, or both.

=Characterization methods=

==X-ray reflectivity (XRR)==

XRR measurements were performed using a Rigaku SmartLab X-ray diffractometer. The Cu X-ray tube was operated at 40 kV and 30 mA. The incident optics included an IPS (incident parallel-slit) adapter with a 5&deg; Soller slit. The slit configuration was IS = 0.05 mm, RS1 = 0.05 mm and RS2 = 0.075 mm. The programmed scan used a step size of 0.01&deg; and a counting time of 2 s per point. The MATLAB analysis reads the actual exported angular coordinates and does not assume a fixed data interval.

==Grazing-incidence X-ray diffraction (GiXRD)==

GiXRD measurements were performed using the Rigaku SmartLab instrument with a Cu sealed X-ray tube operated at 40 kV and 30 mA. The scans covered 30–80&deg; in 2&theta;, using a 0.5 mm incident slit, a step size of 0.01&deg; and a scan speed of 2&deg;/min. The incident angle was fixed at <math>\omega=2^\circ</math> relative to the sample surface.

The shallow fixed incidence increases the film contribution relative to a conventional symmetric scan. Phase assignment is based on the observed reflection series. Reported lattice parameters are approximate because the scans were not subjected to a full instrumental-zero/refraction refinement and the sealed-tube spectrum can contain unresolved Cu K&alpha; contributions.

==Scanning electron microscopy (SEM)==

Plan-view SEM images were recorded at 5.00 kV with the InLens detector. Images were acquired at 200,000&times; and 300,000&times; magnification. The original scale bars and acquisition metadata are retained in the TIFF images.

==Sheet resistance==

Room-temperature sheet resistance was measured for both samples. Resistivity is calculated only for the unbiased sample because only that sample has a defensible XRR thickness.

=Results overview=

{| border="2" cellspacing="2" cellpadding="5" class="wikitable" style="text-align:center;"
|+'''Measured and fitted results'''
|-
! Condition
! Crystalline phase detected by GiXRD
! Lattice parameters from GiXRD
! XRR thickness
! XRR density
! XRR roughness
! Sheet resistance
! Calculated resistivity
|-
| No substrate bias
| <b>V<sub>3</sub>Si, cubic A15</b>
| <math>a=4.731\pm0.003</math> &Aring;<sup>1</sup>
| 94.046 nm
| 4.741 g/cm<sup>3</sup>
| 7.873 nm
| 29.34 &Omega;/sq
| 276 &micro;&Omega;&middot;cm
|-
| 30 W RF substrate bias (69 V DC bias)
| <b>VSi<sub>2</sub>, hexagonal C40</b>
| <math>a=4.574</math> &Aring;, <math>c=6.376</math> &Aring;<sup>1</sup>
| Not obtained; surface too rough for a defensible fit
| Not obtained
| Not obtained
| 6.64 &Omega;/sq
| Not calculated because thickness is unknown
|}

<small><sup>1</sup> Values are derived from pseudo-Voigt fits to several assigned GiXRD reflections using Cu K&alpha;<sub>1</sub> = 1.540593 &Aring;. They should be regarded as approximate GiXRD lattice parameters, not high-resolution lattice refinements.</small>

=Grazing-incidence X-ray diffraction results=

<gallery caption="" widths="850px" heights="600px" perrow="1">
image:eves_GiXRD_V3Si_PC3_bias_comparison_20260916.png|GiXRD comparison of the two PC3 depositions. The temperature shown in the figure is corrected to 600 &deg;C, even though the original data filenames contain 500C.
</gallery>

==Unbiased film: A15 V<sub>3</sub>Si==

The unbiased sample contains the characteristic A15 V<sub>3</sub>Si reflection series. The main fitted peaks are:

{| border="1" cellspacing="1" cellpadding="4" class="wikitable" style="text-align:center;"
|-
! Reflection
! Fitted 2&theta;
! Approximate apparent coherence length<sup>2</sup>
|-
| V<sub>3</sub>Si (200)
| 38.03&deg;
| 13.0 nm
|-
| V<sub>3</sub>Si (210)
| 42.70&deg;
| 10.8 nm
|-
| V<sub>3</sub>Si (211)
| 46.99&deg;
| 14.4 nm
|-
| V<sub>3</sub>Si (320)
| 71.95&deg;
| 16.8 nm
|-
| V<sub>3</sub>Si (321)
| 75.00&deg;
| 12.5 nm
|}

The mean cubic lattice parameter obtained from the five reflections is <math>a=4.731\pm0.003</math> &Aring;. This is slightly larger than the commonly reported room-temperature bulk value of approximately 4.72 &Aring;, but the difference is too small to interpret confidently without a zero-shift/reference correction and a dedicated high-resolution scan.

==30 W RF-biased film: C40 VSi<sub>2</sub>==

The biased sample contains the reflection series expected for C40 VSi<sub>2</sub>. The fitted peaks used for the lattice calculation are:

{| border="1" cellspacing="1" cellpadding="4" class="wikitable" style="text-align:center;"
|-
! Reflection
! Fitted 2&theta;
! Comment
|-
| VSi<sub>2</sub> (110)
| 39.43&deg;
| Isolated peak
|-
| VSi<sub>2</sub> (111)
| 41.96&deg;
| Fitted together with (003)
|-
| VSi<sub>2</sub> (003)
| 42.50&deg;
| Fitted together with (111)
|-
| VSi<sub>2</sub> (112)
| 48.98&deg;
| Several C40 reflections are close in this region
|-
| VSi<sub>2</sub> (031)
| 73.12&deg;
| High-angle constraint
|-
| VSi<sub>2</sub> (032)
| 78.32&deg;
| High-angle constraint
|}

A simultaneous least-squares solution of the hexagonal d-spacing relation gives <math>a=4.574</math> &Aring; and <math>c=6.376</math> &Aring;, in good agreement with reported C40 VSi<sub>2</sub> lattice parameters.

In both samples, “single phase” means that no other crystalline phase was resolved above the detection/background limit within the measured 30–80&deg; range. The scans do not exclude amorphous material, a thin interfacial phase, or a minor crystalline fraction hidden by peak overlap.

<small><sup>2</sup> The coherence lengths are Scherrer estimates based on uncorrected fitted FWHM values. Instrumental broadening, microstrain, texture, peak overlap, and the Cu K&alpha; doublet were not separated. These numbers are therefore approximate coherent-domain sizes and must not be equated directly with SEM surface-feature size.</small>

=X-ray reflectivity results=

<gallery caption="" widths="700px" heights="400px" perrow="1">
image:eves_XRR_V3Si_PC3_bias_comparison_20260916.png|XRR comparison and the exported fit for the unbiased sample. The strong damping/absence of useful fringes from the biased sample prevents a reliable thickness fit.
</gallery>

The unbiased sample could be represented by a simplified single vanadium-silicide layer on Si:

* thickness: 94.046 nm;
* fitted density: 4.741 g/cm<sup>3</sup>;
* fitted layer roughness: 7.873 nm;
* thickness-derived growth rate: 0.0784 nm/s.

The fitted density is about 82% of the 5.77 g/cm<sup>3</sup> bulk value used for V<sub>3</sub>Si. This can reflect porosity/voids, oxidation, model-density/roughness correlation, lateral non-uniformity, or a more complicated interface than the one-layer model. XRR density alone is not a chemical-composition measurement.

The 30 W RF-biased film was too rough for a defensible XRR model. No thickness, density, roughness or resistivity should be quoted from this scan. A cross-sectional measurement is needed.

=SEM surface morphology=

<gallery caption="" widths="800px" heights="570px" perrow="1">
image:eves_SEM_V3Si_PC3_bias_comparison_20260916.png|Plan-view SEM comparison at 200,000&times; and 300,000&times;. Original scale bars and microscope metadata are preserved in each panel.
</gallery>

Both films are rough and polycrystalline, but the morphologies differ strongly:

* the unbiased V<sub>3</sub>Si film consists mainly of much finer, densely distributed granular/nodular surface features, with occasional brighter agglomerates;
* the 30 W-biased VSi<sub>2</sub> film contains substantially larger faceted plate-like grains, many with visible terraces or banded surface contrast;
* the coarser faceted morphology of the biased sample is consistent with its strongly damped XRR response, but plan-view SEM cannot provide an RMS roughness or film thickness.

=Electrical results=

The unbiased V<sub>3</sub>Si sample had a sheet resistance of 29.34 &Omega;/sq. Combining this value with the XRR thickness gives:

<math>
\rho=R_s t
=29.34\ \Omega/\square \times 94.046\ \mathrm{nm}
=276\ \mu\Omega\cdot\mathrm{cm}
</math>

The 30 W-biased VSi<sub>2</sub> sample had a much lower sheet resistance of 6.64 &Omega;/sq, but this does <b>not</b> by itself demonstrate a lower material resistivity or a better film. Sheet resistance depends on both resistivity and thickness. The biased layer may be considerably thicker because of reaction with the Si wafer, may contain an electrically parallel interfacial/unreacted layer, or may simply have a different intrinsic resistivity and connectivity. Until its thickness and cross-sectional structure are measured, only the sheet resistance should be reported.

=Interpretation of the bias-induced phase change=

The most likely working interpretation is that the oxide-stripped Si substrate was an active reactant and that RF substrate bias changed the early interface reaction sufficiently to select a different silicide phase.

# <b>The targets supplied a V-rich flux.</b> The estimated target-derived atomic ratio was V:Si = 4.22, which is more V-rich than V<sub>3</sub>Si. Formation of V<sub>3</sub>Si in the unbiased sample therefore requires some Si uptake from the wafer, but only a modest amount: approximately 11.7 nm of substrate-equivalent Si in the simple full-retention mass balance.
# <b>Bare crystalline Si provides a very large Si reservoir.</b> Earlier V/Si interface studies report that VSi<sub>2</sub> is the first silicide phase to nucleate and grow at a single-crystal Si/V interface. More recent V<sub>3</sub>Si work likewise shows that limiting the available Si favors the V-rich A15 phase, whereas an unrestricted Si supply favors Si-rich silicides.
# <b>The unbiased run may have formed an early V<sub>3</sub>Si-rich reaction layer.</b> With the V-rich incoming flux, such a layer could kinetically limit further Si transport from the wafer and preserve the A15 phase during the remainder of the 1200 s deposition.
# <b>The 69 V substrate DC bias introduced energetic ion bombardment.</b> Ion bombardment can increase defect generation, surface mobility, atomic mixing and re-sputtering. In this experiment it may have disrupted or delayed formation of the V<sub>3</sub>Si-rich barrier, enhanced access to substrate Si, and allowed the thermodynamically/kinetically favored Si-rich VSi<sub>2</sub> reaction to continue. This is a plausible mechanism, not a direct measurement.
# <b>The bias also changed the plasma state.</b> The Si display changed from 100 to 110 V and the V discharge voltage from 322 to 309 V at fixed applied target powers. The actual V and Si arrival rates may therefore have shifted relative to the separate elemental calibrations. Voltage alone is insufficient to calculate the change in composition.

The data demonstrate that 30 W RF substrate bias is not a small microstructural adjustment for this process. On HF-stripped Si at 600 &deg;C it changes the detected crystalline product from V<sub>3</sub>Si to VSi<sub>2</sub> and produces a much coarser surface morphology.

=Limitations=

* Only two depositions were compared; there is no bias-power series and no repeatability test.
* The elemental deposition rates were measured separately, not simultaneously during co-sputtering at 600 &deg;C.
* No direct V:Si composition measurement is available.
* GiXRD establishes crystalline phase identity within its detection limits but does not quantify amorphous material or reliable phase fractions.
* The biased sample has no measured thickness; therefore its resistivity and true deposition/reaction rate are unknown.
* Plan-view SEM does not reveal the film/substrate interface or how much Si was consumed.
* The influence of the HF-to-load delay and any regrown interfacial oxide was not isolated.
* Phase-pure A15 diffraction does not by itself prove superconductivity; a temperature-dependent resistance measurement is required.

=References=

* W. Zhang et al., “Thin-film synthesis of superconductor-on-insulator A15 vanadium silicide,” <i>Scientific Reports</i> 11, 2358 (2021), [https://doi.org/10.1038/s41598-021-82046-1 DOI: 10.1038/s41598-021-82046-1]. This work discusses control of Si supply during V<sub>3</sub>Si formation and provides the V/Si molar-volume calculation used as a cross-check here.
* R. J. Schutz et al., “The formation of vanadium silicides at thin-film interfaces,” <i>Journal of Applied Physics</i> 50, 5773–5781 (1979), [https://doi.org/10.1063/1.326718 DOI: 10.1063/1.326718]. This study reports VSi<sub>2</sub> as the first silicide phase to nucleate and grow at single-crystal Si/V interfaces.
* M. Bose et al., “In-situ Investigation of the Phase Formation and Superconductivity in V<sub>3</sub>Si Thin Films at High Temperatures,” [https://arxiv.org/abs/2412.04159 arXiv:2412.04159]. This work shows that interface/barrier consumption and excessive Si access can drive formation of undesirable Si-rich silicides.
* M. Manzo-Perez et al., “Substrate effects on phase formation and interfacial stability in superconducting vanadium silicide thin films,” <i>Applied Physics Letters</i> 127, 122601 (2025), [https://doi.org/10.1063/5.0291576 DOI: 10.1063/5.0291576].

[[Category:Thin film deposition]]
[[Category:Sputtering]]
[[Category:Vanadium silicide]]
[[Category:Cluster Lesker PC3]]