View source for Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-4/SiO2 Etch

==SiO2 Etch using resist as masking material==
{{CC-bghe2}} <br>
I have do some development of a SiO2 etch with resist as masking material. I have found this fairly good recipe. For now it is the standard SiO2 etch recipes but I might change the "Standard recipe" a a later time if I find a better one. If you need to etch deeper than 1 micrometer then I advise you to split the etch in several runs with O2 cleans in between (3min TDESC Clean) or else it seems like the the etch rate is going down over time.

*[[/SiO2 etch with resist mask|Click here for more results on the process development on SiO2 etch with DUV resist mask]]


<gallery caption="Recipe name: SiO2_res_10, Recipe no. 10: C06445_02 coil_2500W, platen:300W, He/C4F8= 17.5, C4F8/H2=1, Pressure:8.8mTorr, C4F8:25.6sccm, He:448.7sccm, H2:25.6sccm, 3:56 min " perrow="4">

Image:C06445_02_11.jpg|0.4µ/0.2µ<br> Bad lithography
Image:C06445_02_10.jpg|0.5/0.25µ<br> Etch depth: 652 nm<br> Resist left: 456 nm
Image:C06445_02_06.jpg|1µ/0.5µ:<br> Etch depth: 855 nm<br> Resist left: 487 nm
Image:C06445_02_04.jpg|2µ/1µ:<br> Etch depth: 952 nm<br> Resist left: 487 nm
Image:C06445_02_01.jpg|4µ/2µ:<br> Etch depth: 1106 nm<br> Resist left: 487 nm
Image:C06445_02_17.jpg|0.8µ/0.2µ<br> Etch depth: 867 nm<br> Resist left: 426 nm
Image:C06445_02_15.jpg|1.0µ/0.25µ:<br> Etch depth: 893 nm<br> Resist left: 460 nm
Image:C06445_02_13.jpg|4µ/1µ:<br> Etch depth: 1033 nm<br> Resist left: 473 nm

</gallery>

===Uniformity results with SiO2_res_10===
[[File:SiO2 etch uniformity DOE3_10.JPG|400px|thumb|left|Etched for 3min56s, average etch rate: 250 nm/min +- 2.9% ]]
[[File:Contour Plot Y31 EM_02_30 white to blue.jpg|400px|thumb|left|Etched with EM:02/30 for 2min, average etch rate: 275 nm/min +- 4.5%. The electro magnets changed the uniformity pattern and made it a bit worse ]]
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<gallery caption="Recipe name: SiO2_res_10, Recipe no. 10+EM coils: C06445_02 coil_2500W, platen:300W, EM:02/30A, He/C4F8= 17.5, C4F8/H2=1, Pressure:8.8mTorr, C4F8:25.6sccm, He:448.7sccm, H2:25.6sccm, 3:56 min " perrow="5">

File:C09936_05.jpg
File:C09936_04.jpg
File:C09936_03.jpg
File:C09936_02.jpg
File:C09936_01.jpg
</gallery>

Using the electromagnetic coil on the recipe SiO2_res_10 gave higher etch rate on this chip that was placed in the center of a 6" wafer. The Etch profile is more angles. 
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==SiO2 Etch using aSi as masking material==

{{CC-bghe2}} <br>
I am now starting up development of SiO2 etch using aSi as masking material. <br>
The samples I use are: 
*6" Si afters with oxide (2µm), 
*aSi (~300nm),
*Neg. DUV reist (~60nm barc, ~350 nm resist)
*Reticle: Danchip/Triple-D
*Dose 230 J/m2
First I need to make sure that the resist work for pattering the aSi layer is good. If the resist is not good the final etch will also not be good. 

===DUV optimization===
Dose test with the doses (J/m2): 200, 210, 220, 230, 240, 250, 270, 280
The aim was to get good line for 400nm pitch/200nm lines
<gallery caption="400nm pitch 200 nm lines" perrow="5" widths="200px" heights="150px">

Image:dose200_no2_22.jpg |200 J/m2 400nm/268nm
Image:dose210_no2_15.jpg |210 J/m2 400nm/239nm
Image:dose220_no2_13.jpg |220 J/m2 400nm/208nm
Image:dose230_no2_11.jpg |230 J/m2 400nm/209nm
Image:dose240_no2_05.jpg |240 J/m2 400nm/215nm
Image:dose250_no2_11.jpg |250 J/m2 400nm/207nm
Image:dose260_no2_18.jpg |260 J/m2 400nm/188nm
Image:dose270_no2_24.jpg |270 J/m2 400nm/155nm
Image:dose280_no1_15.jpg |280 J/m2 400nm/0nm

</gallery>

<gallery caption="1000nm pitch 500 nm lines" perrow="3" widths="200px" heights="150px">

Image:dose210_no2_17.jpg |210 J/m2 1000nm/581nm
Image:dose230_no2_12.jpg |230 J/m2 1000nm/517nm
Image:dose240_no2_03.jpg |240 J/m2 1000nm/518nm
Image:dose250_no2_09.jpg |250 J/m2 1000nm/510nm
Image:dose260_no2_15.jpg |260 J/m2 1000nm/493nm
Image:dose270_no2_22.jpg |270 J/m2 1000nm/494nm

</gallery>


==Testing with electromagnetic coils==
{{CC-bghe2}} <br>

When testing with decreased platen power on the SiO2_10 standard recipe the uniformity got very bad. I then tested with the electromagnetics coil to see if that could affect the uniformity. There is an outer coil that can be varied between 0 A and 10 A and an inner coil that can be varied between 0 A and 30 A. The first tests were done on Si/SiO2(1µm) without pattern and measured on the ellipsometer. 
{| border="2" cellspacing="2" cellpadding="3" 
!Parameter
|Recipe name: '''no 10 with lower platen power'''
  
|-
|Coil Power [W]
|2500

|-
|Platen Power [W]
|200

|-
|Platen temperature [<sup>o</sup>C]
|20

|-
|H2 flow [sccm]
|25.6

|-
|C<sub>4</sub>F<sub>8</sub> flow [sccm]
|25.6

|-
|He flow [sccm]
|448.7

|-
|Pressure 
|Fully open APC valve (8-9 mTorr)

|-
|Electromagnetic coils (EM) 'outer coil' / 'inner coil'
|'0-10 A' / '0-30 A'

|-
|}

<gallery caption="EM tests" perrow="3" widths="400px" heights="300px">
File:Contour Plot Y15 EM_0_0.JPG| Etch time: 2 min, Average etch rate: 100.2 nm/min, range:+-55.1%  
File:Contour Plot Y16 EM_10_30.JPG|Etch time: 2 min, Average etch rate: 100.5 nm/min, range:+-32.6%  
File:Contour Plot Y27 EM_10_0.JPG|Etch time: 2 min, Average etch rate: 100.8 nm/min, range:+-50.8%  
File:Contour Plot Y26 EM_0_30.JPG|Etch time: 2 min, Average etch rate: 203.8 nm/min, range:+-6.1%  
File:Contour Plot Y29 EM_2_30.JPG|Etch time: 2 min, Average etch rate: 186.2 nm/min, range:+-3.2%  
File:Contour Plot patterned wafer EM_2_30.JPG| Etch time: 6 min on patterned wafer with different measurement points, <100 nm Cr mask is still on, EM_2/30, Average etch rate: 207-223 nm/min depending on how much Cr mask is left, range:+-2.3%  
</gallery>