LabAdviser/Technology Research/Technology Development of 3D Silicon Plasma Etching process for Novel Devices and Applications: Difference between revisions
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'''Feedback to this page''': '''[mailto:labadviser@ | '''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/LabAdviser/Technology_Research/Technology_Development_of_3D_Silicon_Plasma_Etching_process_for_Novel_Devices_and_Applications click here]''' | ||
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*'''Project responsible:''' Bingdong Chang | *'''Project responsible:''' Bingdong Chang | ||
*'''Supervisors:'''Henri Jansen, Flemming Jensen, Jörg Hübner | *'''Supervisors:'''Henri Jansen, Flemming Jensen, Jörg Hübner | ||
*'''Partners involved:''' DTU Danchip | *'''Partners involved:''' DTU Nanolab (former DTU Danchip) | ||
*'''Full Thesis''': https://orbit.dtu.dk/en/publications/technology-development-of-3d-silicon-plasma-etching-processes-for | |||
==Project Description== | ==Project Description== | ||
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Although widely utilized and largely understood, silicon etch processes fail to reproduce at the nanoscale. Transport effects ‘down the etched cavity’ limit rate and selectivity while aspect ratios, profile and passivation control are more challenging. For example, aspect ratios beyond 30 are rarely utilized and fluctuations in the results are common. So, at the nanoscale, etching becomes more difficult. Basically, two types of etching techniques can be distinguished; the continuous (or mixed) process and the alternating (or pulsed/Bosch) process. The continuous process generally has smooth sidewalls and low undercut and it is the standard technique in mainstream nano-electronic chip fabrication. However, at room temperature the mixed gas process, results in a low rate selectivity and aspect ratio capability – as such it is limited to shallow features. The alternating etch process is probably the most popular technique in MEMS production facilities today. It uses a repeating sequence of plasma enhanced deposition to passivate silicon features, a physical etch for directional removal of this layer at the base of the features, and an isotropic etch for silicon removal at the cleared surfaces. However, it is not well suited to the nanoscale due to finite sidewall scallop size and undercut unless rate and selectivity are severely compromised. Typically it is not applied below 500nm trench feature sizes – although 100nm features have been demonstrated. | Although widely utilized and largely understood, silicon etch processes fail to reproduce at the nanoscale. Transport effects ‘down the etched cavity’ limit rate and selectivity while aspect ratios, profile and passivation control are more challenging. For example, aspect ratios beyond 30 are rarely utilized and fluctuations in the results are common. So, at the nanoscale, etching becomes more difficult. Basically, two types of etching techniques can be distinguished; the continuous (or mixed) process and the alternating (or pulsed/Bosch) process. The continuous process generally has smooth sidewalls and low undercut and it is the standard technique in mainstream nano-electronic chip fabrication. However, at room temperature the mixed gas process, results in a low rate selectivity and aspect ratio capability – as such it is limited to shallow features. The alternating etch process is probably the most popular technique in MEMS production facilities today. It uses a repeating sequence of plasma enhanced deposition to passivate silicon features, a physical etch for directional removal of this layer at the base of the features, and an isotropic etch for silicon removal at the cleared surfaces. However, it is not well suited to the nanoscale due to finite sidewall scallop size and undercut unless rate and selectivity are severely compromised. Typically it is not applied below 500nm trench feature sizes – although 100nm features have been demonstrated. | ||
The major part of this project will be related to experimental work in the cleanroom facility at DTU Danchip. It is the quest to develop a fundamental understanding of the special challenges involved in dry etching at the nanoscale including the physics and chemistry involved in the processing. The aim is to establish a generic knowledge platform for the nanoscale dry etching for future applications. An important part of the project will be to demonstrate the ability of 3D plasma etching technology in both micro- and nanoscale. | The major part of this project will be related to experimental work in the cleanroom facility at DTU Nanolab (former DTU Danchip). It is the quest to develop a fundamental understanding of the special challenges involved in dry etching at the nanoscale including the physics and chemistry involved in the processing. The aim is to establish a generic knowledge platform for the nanoscale dry etching for future applications. An important part of the project will be to demonstrate the ability of 3D plasma etching technology in both micro- and nanoscale. | ||
Firstly, the applications of 3D silicon structures will be explored for nanophotonics study, e.g. deep subwavelength scattering of silicon nanostructures and photonic crystals, or photonic bandgap (PBG) structures. Since previous studies are mostly focused in 1D or 2D structures, e.g. planar waveguides, distributed Bragg reflectors, etc, while 3D structures can provide possibility to control and manipulate light in all three spatial dimensions. The fabrication of 3D silicon nanostructures, however, is difficult with traditional techniques and the structure quality is limited. In this study, 3D silicon nanostructures (e.g. vertically stacked silicon nanowires, 3D silicon simple cubic structures) will be fabricated and the optical properties will be characterized. | Firstly, the applications of 3D silicon structures will be explored for nanophotonics study, e.g. deep subwavelength scattering of silicon nanostructures and photonic crystals, or photonic bandgap (PBG) structures. Since previous studies are mostly focused in 1D or 2D structures, e.g. planar waveguides, distributed Bragg reflectors, etc, while 3D structures can provide possibility to control and manipulate light in all three spatial dimensions. The fabrication of 3D silicon nanostructures, however, is difficult with traditional techniques and the structure quality is limited. In this study, 3D silicon nanostructures (e.g. vertically stacked silicon nanowires, 3D silicon simple cubic structures) will be fabricated and the optical properties will be characterized. | ||
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==Galleries== | ==Galleries== | ||
Below are images illustrating works that have been done during the ph.d. projects. | |||
<gallery caption=" | <gallery caption="" widths="380px" heights="300px" perrow="3"> | ||
image:3D_PhC.png| 3D silicon photonic crystal membranes. | image:3D_PhC.png| 1. 3D silicon photonic crystal membranes. | ||
image: | image:Scallops.png| 2. Comparison of scallops by traditional Bosch process and modified DREM process. | ||
image: | image:3Dmicro.png| 3. 3D silicon microstructures fabricated by DREM process. | ||
image: | image:SiZnO.png| 4. 3D silicon micro-mesh structures integrated with ZnO nanowires for photocatalysis and photocurrent generation. | ||
image:SiNanoColor.png| 5. 3D silicon stacked nanowires for structural color generation. | |||
image:SiMicroPillars.png| 6. High aspect ratio silicon micropillars fabricated with DREM process. | |||
image:ZIF8.png| 7. ZIF-8 crystals for tunable structural colors. | |||
image:FConPegasus.png| 8. Using OES to monitor the fluorocarbon film deposition with Pegasus 1. | |||
</gallery> | </gallery> | ||