Specific Process Knowledge/Etch/III-V ICP/InP-InGaAsP-InGaAs: Difference between revisions

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Image:S0_oxide_05.jpg|Sample S0: Top view of the oxide mask before etching. It is the TRAVKA50 mask, but it is clear that the CD reduction is about the 1-1.5 µm of the lines.
Image:S0_oxide_05.jpg|Sample S0: Top view of the oxide mask before etching. It is the TRAVKA50 mask, but it is clear that the CD reduction is about the 1-1.5 µm of the lines.
Image:S4_06.jpg|Sample S4: Profile view. The recipe InP etch has been used. <br> The sample has been run on a SiO2 carrier wafer. <br> There is not much CD change compared to the oxide mask before the etch. <br> It seems like the SiO2 mask is gone and the sidewall angle from the mask has been transferred into the sample. <br> The sidewall profile is quit vertical in the lower part.
Image:S4_06.jpg|Sample S4: Profile view. The recipe InP etch has been used. <br> The sample has been run on a SiO2 carrier wafer. <br> There is not much CD change compared to the oxide mask before the etch. <br> It seems like the SiO2 mask is gone and the sidewall angle from the mask has been transferred into the sample. <br> The sidewall profile is quit vertical in the lower part. <br> Etch time 15 min
Image:S5_05.jpg|Sample S5: Profile view. The recipe InP etch has been used but with modified Cl2 and N2 flows: N"=30 sccm Cl2=30 sccm. <br> The sample has been run on a SiO2 carrier wafer. <br> There is not much CD change compared to the oxide mask before the etch. <br> It seems like the SiO2 mask is gone. <br> the sidewall profile is overcutting probably due to too little passivation.
Image:S5_05.jpg|Sample S5: Profile view. The recipe InP etch has been used but with modified Cl2 and N2 flows: N"=30 sccm Cl2=30 sccm. <br> The sample has been run on a SiO2 carrier wafer. <br> There is not much CD change compared to the oxide mask before the etch. <br> It seems like the SiO2 mask is gone. <br> the sidewall profile is overcutting probably due to too little passivation. <br> Etch time 10 min
Image:none
Image:none
Image:S4_30dg_2_05.jpg|Sample S4: The sidewall roughness on the sample S4 is quit high
Image:S4_30dg_2_05.jpg|Sample S4: The sidewall roughness on the sample S4 is quit high

Revision as of 08:51, 2 July 2018

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InP/InGaAsP/InGaAs etch

Unselective etch for large sized features and small aspect ratios by David Larsson, DTU Photonics, 2011

Recipe InP Etch 1/InP Precond 1
Cl2 flow 20 sccm
N2 flow 40 sccm
Ar flow 10 sccm
Platen power 100 W
Coil power 500 W
Pressure 2 mTorr
Platen chiller temperature 180 oC
Comment Use SiO2 carrier (not Si) (Kabi/Bghe June 2018)


Results (InP Etch 1)
Etch rate 500-600 nm/min
Sidewall angle 86-87 o
Selectivity (InP:SiO2, InP:HSQ) 50:1

InP etching June 2018

Done by Kabi and Bghe @danchip

Sample pattern before etching

Etching of an InP piece on Si carrier

InP piece patterned with SiO2. The piece was etched on top of a Si wafer without bonding. The recipe "InP etch" was used. The roughness looks high in the bottom of the etched areas, especially in the large open areas.

Etching of an InP piece on SiO2 carrier

InP piece patterned with SiO2. The piece was etched on top of a Si wafer coated with SiO2 without bonding. The recipe "InP etch" was used. The roughness looks low in the bottom of the etched areas, even in the large open areas.


Changing the Cl2/N2 ratio