Specific Process Knowledge/Etch/DRIE-Pegasus

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The DRIE Pegasus tools at Danchip

In 2010 Danchip acquired DRIE-Pegasus 1 (at the time called DRIE-Pegasus). As a state-of-the-art etch tool with excellent performance and great flexibility, it grew immensely popular and by 2015 it was apparent that we needed yet another tool to cope with the demand. Therefore, in 2016 Pegasus 2 was acquired from a closed-down lab in Morocco and installed next to Pegasus 1.

Looking to expand our dry etching capabilities in 2017 we got an irresistible offer on a twin Pegasus system with cassette to cassette vacuum robot from a commerciel fab. The twin Pegasus system (will be called Pegasus 3 and 4) will be installed at the old cluster 2 location in cleanroom C1 from August 2018 onwards. We intend to use one chamber as 6" silicon etch work horse and the other to be converted (adding extra process gases) into a 6" dielectric etch tool that will supplement/replace the AOE.

The DRIE-Pegasus 1 load lock and cassette loader in the Danchip cleanroom A-1	The-Pegasus 2 operator station and load lock in the Danchip cleanroom A-1
DRIE-Pegasus 1	DRIE-Pegasus 2
Serial MP0636	Serial MP0641

The Bosch process

The DRIE Pegasus tools are state-of-art silicon dry etchers that offer outstanding performance in terms of etch rate, uniformity etc. They use the so-called Bosch process to achieve excellent control of the etched features. Click HERE for more fundamental information of the system. As of 2017, completing the Dry Etch TPT course is mandatory for all new users. On the TPT web page you will find a version of the latest lecture slides - here you will find information as well.

Links to the individual pages for the Pegasi

• DRIE-Pegasus 1
• DRIE-Pegasus 2
• DRIE-Pegasus 3 - installation in progress
• DRIE-Pegasus 4 - installation in progress

Equipment performance and process related parameters

Equipment		DRIE-Pegasus 1	DRIE-Pegasus 2	DRIE-Pegasus 3	DRIE-Pegasus 4
Purpose	Primary	Dry etching of 4" silicon Dry etching of barc	Research tool	Dry etching of 6" silicon	Dry etching of 6" dielectrics
	Alternative	Black silicon	Backup dry etching of 6" silicon	?	?
Performance	Etch rates	Standard processes A and B up to 15 µm/min depending on etch load and feature size Other processes: Any number from 200 nm/min to 10 µm/min	?	?	?
	Uniformity	For standard processes better than 3 % across a 150 mm wafer.	?	?	?
Process parameter range	RF powers	Coil Power 5 kW Platen power 300/500 W (HF/LF)	Coil Power 5 kW Platen power 300/500 W (HF/LF)	Coil Power 5 kW Platen power 300/500 W (HF/LF)	Coil Power 5 kW Platen power 300/500 W (HF/LF)
	Gas flows	SF6: 0 to 1200 sccm O2: 0 to 200 sccm C4F8: 0 to 400 sccm Ar: 0 to 283 sccm	SF6: 0 to 1200 sccm O2: 0 to 200 sccm C4F8: 0 to 400 sccm Ar: 0 to 283 sccm	SF6 O2 C4F8 Ar	SF6 O2 C4F8 Ar He CF4 H2
	Pressure and temperature	Pressure range 4 to 250 mTorr Temperature range -20 to 30 degrees C	Pressure range 4 to 250 mTorr Temperature range -20 to 30 degrees C	Pressure range 4 to 250 mTorr Temperature range -20 to 30 degrees C	Pressure range 4 to 250 mTorr Temperature range -20 to 30 degrees C
	Process options	Bosch processes with etch and dep cycles each split into three Parameter ramping during process steps SOI option to reduce notching at buried Picoscope monitoring Claritas endpoint detection system	Bosch processes with etch and dep cycles each split into three Parameter ramping during process steps SOI option to reduce notching at buried Picoscope monitoring Verity OES	Bosch processes with etch and dep cycles each split into three Parameter ramping during process steps	Bosch processes with etch and dep cycles each split into three Parameter ramping during process steps
Substrates	Sizes	Smaller than 100mm: Bonded to carriers 100 mm wafers: Up to 25 wafers in a batch process	Smaller than 150mm: Bonded to carriers 150 mm wafers	Smaller than 150mm: Bonded to carriers 150 mm wafers	Smaller than 150mm: Bonded to carriers 150 mm wafers
	Loading	Load lock MACS	Load lock	Vacuum cassette loader	Vacuum cassette loader
	Allowed materials	Silicon wafers Quartz wafers need a (semi)conducting layer for clamping	Silicon wafers Quartz wafers need a (semi)conducting layer for clamping	Silicon wafers Quartz wafers need a (semi)conducting layer for clamping	Silicon wafers Quartz wafers need a (semi)conducting layer for clamping
	Possible masking materials	AZ photoresist zep resist DUV stepper resist (barc + krf) Oxides and nitrides Aluminium (only very gentle processes such as process C and nanoetches)	AZ photoresist zep resist DUV stepper resist (barc + krf) Oxides and nitrides Aluminium (only very gentle processes)	AZ and MiR photoresist zep resist DUV stepper resist (barc + krf) Oxides and nitrides	AZ photoresist zep resist DUV stepper resist (barc + krf) Oxides and nitrides

General Pegasus information

Wafer bonding

To find information on how to bond wafers or chips to a carrier wafer, click here.

Characterisation of etched trenches

Comparing differences in etched trenches requires a set of common parameters for each trench. Click here to find more information about the parameters used on the DRIE-Pegasus process development.

Material from SPTS

• Hardware and process applications

• Miscellaneous information