Specific Process Knowledge/Thermal Process/C3 Anneal-bond furnace: Difference between revisions

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''This page is written by DTU Nanolab  internal''
[[Category: Equipment |Thermal C3]]
[[Category: Thermal process|C3]]
[[Category: Furnaces|C3]]


==Anneal-bond furnace (C3)==
==Anneal-bond furnace (C3)==
[[Image:C3.JPG|thumb|300x300px|Anneal-bond furnace (C3). Positioned in cleanroom 2]]
[[Image:C3.JPG|thumb|300x300px|Anneal-bond furnace (C3). Positioned in cleanroom B-1/ Photo: DTU Nanolab internal]]


The Anneal-bond furnace (C3) is a Tempress horizontal furnace for oxidation and annealing of new and processed (bonded) silicon wafers.
The Anneal-bond furnace (C3) is a Tempress horizontal furnace for oxidation and annealing of new and processed (e.g. bonded) silicon wafers. O<sub>2</sub>) is used as an oxidant for dry oxidation, and for wet oxidation water vapour is being generated by a bubbler.  


This furnace is the third furnace tube in the furnace C-stack positioned in cleanroom 2.  
This furnace is the third tube in the furnace C-stack positioned in cleanroom B-1.
 
In this furnace it is allowed oxidize and anneal new wafers without doing an RCA clean first. Also silicon wafers from PECVD4 and wafers without any metal coming from PECVD3 and bonded wafers comming directly from the Wafer Bonder 02 (assuming they were clean and not have been exposed to any metal when entering wafer bonder) can be processed in the furnace without an RCA cleaning. Check the cross contamination information in LabManager before you use the furnace.


In this furnace it is allowed oxidize and anneal wafers without doing an RCA clean first. Also bonded wafers comming directly from the EVG NIL (assuming they were clean and not have been exposed to any metal when entering EVG NIL) can be processed in the furnace. Check the cross contamination information in LabManager before you use the furnace.


'''The user manual, technical information and contact information can be found in LabManager:'''
'''The user manual, technical information and contact information can be found in LabManager:'''


'''[http://www.labmanager.danchip.dtu.dk/function.php?module=Machine&view=view&mach=89 Anneal-bond Furnace (C3)]'''
'''[http://www.labmanager.danchip.dtu.dk/function.php?module=Machine&view=view&mach=89 Anneal-bond Furnace (C3)]'''


==Process knowledge==
==Process knowledge==
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*Annealing: look at the [[Specific Process Knowledge/Thermal Process/Annealing|Annealing]] page
*Annealing: look at the [[Specific Process Knowledge/Thermal Process/Annealing|Annealing]] page


==Overview of the performance of Anneal Bond furnace and some process related parameters==
 
==Overview of the performance of the Anneal Bond furnace (C3) and some process related parameters==


{| border="2" cellspacing="0" cellpadding="2"  
{| border="2" cellspacing="0" cellpadding="2"  
Line 26: Line 34:
*Oxidation of Si wafers
*Oxidation of Si wafers
*Annealing of processed wafers, eg. bonded wafers from EVG NIL
*Annealing of processed wafers, eg. bonded wafers from EVG NIL
|style="background:WhiteSmoke; color:black"|Oxidation:
|style="background:WhiteSmoke; color:black"|
*Dry
Annealing:
*Wet: with bubbler (water steam + O<sub>2</sub>)
*Using N<sub>2</sub>
Oxidation:
*Dry oxidation using O<sub>2</sub>
*Wet oxidation using H<sub>2</sub>O vapour generated by a bubbler
|-
|-
!style="background:silver; color:black" align="center"|Performance
!style="background:silver; color:black" align="center"|Performance
|style="background:LightGrey; color:black"|Film thickness
|style="background:LightGrey; color:black"|Film thickness
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*Dry SiO<sub>2</sub>: 50 Å to ~2000 Å (it takes too long to grow a thicker oxide)
*Dry oxide:~ 0 nm to 300 nm (it takes too long to grow thicker dry oxide layers)
*Wet SiO<sub>2</sub>: 50 Å to ~5 µm (it takes too long to grow a thicker oxide)
*Wet oxide: ~ 0 nm to 3 µm (23 hours wet oxidation at 1100 <sup>o</sup>C)
|-
|-
!style="background:silver; color:black" align="center" valign="center" rowspan="3"|Process parameter range
!style="background:silver; color:black" align="center" valign="center" rowspan="3"|Process parameter range
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|style="background:LightGrey; color:black"|Process pressure
|style="background:LightGrey; color:black"|Process pressure
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*1 atm
*1 atm (no vacuum)
|-
|-
|style="background:LightGrey; color:black"|Gas flows
|style="background:LightGrey; color:black"|Gas flows
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*N<sub>2</sub>: 10 slm  
*N<sub>2</sub>: 0-10 slm  
*O<sub>2</sub>: 10 slm  
*O<sub>2</sub>: 0-10 slm  
|-
|-
!style="background:silver; color:black" align="center" valign="center" rowspan="2"|Substrates
!style="background:silver; color:black" align="center" valign="center" rowspan="2"|Substrates
|style="background:LightGrey; color:black"|Batch size
|style="background:LightGrey; color:black"|Batch size
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*1-30 100 mm wafers (or 50 mm wafers) per run
*1-30 100 mm wafers (or 50 mm wafers)  
|-
|-
|style="background:LightGrey; color:black"|Substrate materials allowed
|style="background:LightGrey; color:black"|Substrate materials allowed
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*Silicon wafers (new wafers or RCA cleaned wafers)
*Silicon wafers  
*Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned)
*Silicon wafers with layers of silicon oxide or silicon nitride  
*Wafers from the LPCVD furnaces
*Wafers from the LPCVD furnaces
*Wafers from EVG NIL (assuming they were clean and not have been exposed to any metal when entering the EVG NIL)
*Wafers from PECVD4
*Wafers from PECVD3 (without any metal)
*Wafers from Wafer Bonder 02 (assuming they were clean and not have been exposed to any metal when entering the Wafer Bonder 02)
|-  
|-  
|}
|}

Latest revision as of 14:22, 31 January 2023

Feedback to this page: click here

This page is written by DTU Nanolab internal

Anneal-bond furnace (C3)

Anneal-bond furnace (C3). Positioned in cleanroom B-1/ Photo: DTU Nanolab internal

The Anneal-bond furnace (C3) is a Tempress horizontal furnace for oxidation and annealing of new and processed (e.g. bonded) silicon wafers. O2) is used as an oxidant for dry oxidation, and for wet oxidation water vapour is being generated by a bubbler.

This furnace is the third tube in the furnace C-stack positioned in cleanroom B-1.

In this furnace it is allowed oxidize and anneal new wafers without doing an RCA clean first. Also silicon wafers from PECVD4 and wafers without any metal coming from PECVD3 and bonded wafers comming directly from the Wafer Bonder 02 (assuming they were clean and not have been exposed to any metal when entering wafer bonder) can be processed in the furnace without an RCA cleaning. Check the cross contamination information in LabManager before you use the furnace.


The user manual, technical information and contact information can be found in LabManager:

Anneal-bond Furnace (C3)


Process knowledge


Overview of the performance of the Anneal Bond furnace (C3) and some process related parameters

Purpose
  • Oxidation of Si wafers
  • Annealing of processed wafers, eg. bonded wafers from EVG NIL

Annealing:

  • Using N2

Oxidation:

  • Dry oxidation using O2
  • Wet oxidation using H2O vapour generated by a bubbler
Performance Film thickness
  • Dry oxide:~ 0 nm to 300 nm (it takes too long to grow thicker dry oxide layers)
  • Wet oxide: ~ 0 nm to 3 µm (23 hours wet oxidation at 1100 oC)
Process parameter range Process temperature
  • 800-1150 oC
Process pressure
  • 1 atm (no vacuum)
Gas flows
  • N2: 0-10 slm
  • O2: 0-10 slm
Substrates Batch size
  • 1-30 100 mm wafers (or 50 mm wafers)
Substrate materials allowed
  • Silicon wafers
  • Silicon wafers with layers of silicon oxide or silicon nitride
  • Wafers from the LPCVD furnaces
  • Wafers from PECVD4
  • Wafers from PECVD3 (without any metal)
  • Wafers from Wafer Bonder 02 (assuming they were clean and not have been exposed to any metal when entering the Wafer Bonder 02)
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