Specific Process Knowledge/Etch/ASE (Advanced Silicon Etch): Difference between revisions

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= The ASE =
'''Feedback to this page''': '''[mailto:labadviser@Nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.Nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ASE_(Advanced_Silicon_Etch) click here]'''


[[image:ASE.jpg|200x200px|right|thumb|The ICP-DRIE tool at Danchip: STS ASE - positioned in cleanroom2]]
[[Category: Equipment |Etch ASE]]
[[Category: Etch (Dry) Equipment|ASE]]
<!--Checked for updates on 28/6-2023 - ok/jmli -->


The ICP-DRIE (Inductively Coupled Plasma - Deep Reactive Ion Etcher) tool at Danchip is manufactured by STS and is called the ASE (Advanced Silicon Etcher). The main purpose of the ASE is etching of silicon using Bosch process.
{{Contentbydryetch}}


==The Bosch process: Etching of silicon==
= The ASE =
 
The Bosch process uses alternation between an etch cycle and a passivation cycle. Introducing a passivation step in an etch process is very beneficial for the control of the angle of the sidewalls in the etch process because it allows us to cover them with a protective layer that suppresses the isotropic etching. Combined with the high plasma density in the ICP chamber, the excellent sidewall control enables us to etch high aspect ratio structures in silicon with very high etch rates.


In the case of the silicon etching on the ASE, an etch phase with SF<sub>6</sub> and O<sub>2</sub> alternates with a passivation phase with C<sub>4</sub>F<sub>8</sub>.
[[image:ASE.jpg|300x300px|right|thumb|STS ASE - positioned in cleanroom B-1. {{photo1}} ]]


=== The two standard silicon etch recipes ===
Name: M/PLEX ICP - ASE (Advanced Silicon Etcher) <br>
Vendor: STS (now SPTS) <br>
The ASE was the first ICP (Inductively coupled plasma) tool at DTU Nanolab. It was manufactured by STS and is called the ASE (Advanced Silicon Etcher). Originally the main purpose of the ASE was etching of silicon using the Bosch process. However, after the acquisition of the [[Specific Process Knowledge/Etch/DRIE-Pegasus|DRIE-Pegasus]] and the retirement of our old RIE's the ASE will only serve as a "dirty" plasma etcher, etching silicon, Silicon oxide and silicon nitride on wafers with small amount of metals exposed and as a polymer etcher. The rule is that samples with up to 4 cm2 of metal on the surface will be allowed to process. Extra gasses was been added to the machine to allow SiO2 and SiN etching. Using these gasses may affect the conditioning of the chamber and thereby the stability of processes. Any clean processes and sensitive processes should take place in to the DRIEs or elsewhere.


Two recipes have been optimized for the ASE. Their specification is on a 10 % etch load wafer with trenches.
* '''Shallolr''': The shallow etch process will etch a 2 <math>\mu</math>m opening down to make a 20 <math>\mu</math>m trench.
* '''Deepetch''': The deep etch process will etch a 50 <math>\mu</math>m opening down to make a 300 <math>\mu</math>m trench.
The standardization procedure on the ASE covers these two etches.


== Recipes on the ASE ==
In the case of the silicon etching on the ASE, an etch phase with SF<sub>6</sub> and O<sub>2</sub> alternates with a passivation phase with C<sub>4</sub>F<sub>8</sub>.
 
=== Shallolr ===
 
The shallolr recipe is designed to etch features (with sizes above 1 <math>\mu</math>m) in silicon down to a depth that ranges from a few microns to some 50 microns. (If you need to etch deeper use Deepetch or more shallow, see Nanoetches.) It is specified to etch a 2 <math>\mu</math>m wide trench down to a depth of 20 <math>\mu</math>m on a wafer that has a global/local etch opening density of 10%.
 
The recipe is given below.
 
{| border="2" cellpadding="2" cellspacing="1"
|+ The shallolr recipe
|-
! colspan="2" align="center"| Common parameters
! colspan="3" align="center"| Multiplexed parameters
|-
! Parameter 
! Setting
! Parameter
! Etch
! Passivation
|-
! Temperature
| 10<sup>o</sup>C
! SF<sub>6</sub> Flow
| 260 sccm
| 0 sccm
|-
! No. of cycles
| 31
! O<sub>2</sub> Flow
| 26 sccm
| 0 sccm
|-
! Process time
| 5:56 mins
! C<sub>4</sub>F<sub>4</sub> Flow
| 0 sccm
| 120 sccm
|-
! APC mode
| manual
! RF coil
| 2800 W
| 1000 W
|-
! APC setting
| 86.8 %
! RF Platen
| 16 W
| 0 W
|-
!
|
! Cycle time
| 6.5 s
| 5 s
|}
 
The process runs for 31 cycles (5:56 mins). The fact that it's Bosch process is clear from the scallops on the sidewalls - one should be able to count 31 of them.  


<gallery caption="Standardization images of the shallolr recipe" widths="300px" heights="300px" perrow="2">
'''The user manual, quality control procedure and results, user APV(s), technical information and contact information can be found in LabManager:'''
Image:jmlshal070921 pos1 2mu_09.jpg|The profile of a 2 <math>\mu</math>m trench
image:jmlshal070921 pos1 50mu_08.jpg|The profile of a 50 <math>\mu</math>m trench
</gallery>


The process is designed to reach 20 <math>\mu</math>m down in a 2 <math>\mu</math>m trench but as is clear from the image of the corresponding 50 <math>\mu</math>m trench, this one is etched deeper. The reason is the so called Aspect Ratio Dependent Etching or ARDE: See below.
Equipment info in [http://labmanager.dtu.dk/function.php?module=Machine&view=view&mach=105| LabManager]


=== Deepetch ===
==Process information==
*[[Specific Process Knowledge/Etch/Etching of Silicon/Si etch using ASE|Etch of Silicon using ASE]]
*[[Specific Process Knowledge/Etch/Etching of Polymer/Polymer Etch by ASE|Etch of polymers using ASE]]
*[[Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using ASE|Etch of SiO2/SiN using ASE]]


The deepetch recipe is designed to etch features (with sizes 2 <math>\mu</math>m) in silicon down to a depth that ranges from some 50 microns to hundreds of microns. (If you need to etch less, use shallow or Nanoetches.) It is specified to etch a 50 <math>\mu</math>m wide trench down to a depth of 300 <math>\mu</math>m on a wafer that has a global/local etch density of 10%.
==An overview of the performance of the ASE and some process related parameters==


The recipe is given below.
{| border="2" cellspacing="0" cellpadding="2"  
 
{| border="2" cellpadding="2" cellspacing="1"  
|+ The deepetch recipe
|-
! colspan="2" align="center"| Common parameters
! colspan="3" align="center"| Multiplexed parameters
|-
|-
! Parameter 
!style="background:silver; color:black;" align="left"|Purpose
! Setting
|style="background:LightGrey; color:black"|Dry etch of
! Parameter
|style="background:WhiteSmoke; color:black"|
! Etch
* Silicon
! Passivation
*Thin layers of Silicon oxide and silicon nitride
* Polymers such as polyimide, PDMS, PMMA, BCB and resists
|-
|-
! Temperature
!style="background:silver; color:black" align="left" valign="top" rowspan="2"|Performance
| 20<sup>o</sup>C
|style="background:LightGrey; color:black"|Etch rates
! SF<sub>6</sub> Flow
|style="background:WhiteSmoke; color:black"|
| 230 sccm
*Silicon: ~0-15 µm/min (depending on features size and etch load)
| 0 sccm
*Silicon oxide: <0.1 µm/min
*Silicon nitride: <0.1 µm/min
|-
|-
! No. of cycles
|style="background:LightGrey; color:black"|Anisotropy
| 250
|style="background:WhiteSmoke; color:black"|
! O<sub>2</sub> Flow
*Good
| 23 sccm
| 0 sccm
|-
|-
! Process time
!style="background:silver; color:black" align="left" valign="top" rowspan="2"|Process parameter range
| 54:10 mins
|style="background:LightGrey; color:black"|Process pressure
! C<sub>4</sub>F<sub>4</sub> Flow
|style="background:WhiteSmoke; color:black"|
| 0 sccm
*~0.1-95 mTorr
| 120 sccm
|-
|-
! APC mode
|style="background:LightGrey; color:black"|Gas flows
| manual
|style="background:WhiteSmoke; color:black"|
! RF coil
*SF<sub>6</sub>: 0-600 sccm
| 2800 W
*O<sub>2</sub>: 0-99 sccm
| 1000 W
*C<sub>4</sub>F<sub>8</sub>: 0-300 sccm
*Ar: 0-142 sccm
*CF<sub>4</sub>: 0-99.9 sccm
*CHF<sub>3</sub>: 0-99.9 sccm
*H<sub>2</sub>: 0-40 sccm
*He: 0-500 sccm
|-
|-
! APC setting
!style="background:silver; color:black" align="left" valign="top" rowspan="3"|Substrates
| 87.7 %
|style="background:LightGrey; color:black"|Batch size
! RF Platen
|style="background:WhiteSmoke; color:black"|
| 19 W
*1 4" wafer per run
| 0 W
*1 2" wafer per run (requires carrier)
*Or several smaller pieces on a carrier wafer
|-
|-
!
| style="background:LightGrey; color:black"|Substrate material allowed
|
|style="background:WhiteSmoke; color:black"|
! Cycle time
*Silicon wafers
| 8 s
**with layers of silicon oxide or silicon (oxy)nitride
| 5 s
*Quartz wafers
|-
| style="background:LightGrey; color:black"|Possible masking material
|style="background:WhiteSmoke; color:black"|
*Photoresist/e-beam resist
*PolySilicon
*Silicon oxide or silicon (oxy)nitride
*Aluminium
|-
|}
|}
<gallery caption="Standardization images of the deepetch recipe" widths="300px" heights="300px" perrow="2">
Image:jmldeep071101 pos1 2mu_010.jpg|The profile of a 2 <math>\mu</math>m trench
image:jmldeep071101 pos5 50mu_013.jpg|The profile of a 50 <math>\mu</math>m trench
</gallery>
As is clear from the two images ARDE also plays a role in this case: The 2 <math>\mu</math>m trench (widened to about 5-6 <math>\mu</math>m because of undercut/underetching) is only etched 150 <math>\mu</math>m.
== Standardization procedure on the ASE ==

Latest revision as of 09:15, 1 September 2023

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Unless otherwise stated, the content of this page was created by the dry etch group at DTU Nanolab

The ASE

STS ASE - positioned in cleanroom B-1. Photo: DTU Nanolab internal

Name: M/PLEX ICP - ASE (Advanced Silicon Etcher)
Vendor: STS (now SPTS)
The ASE was the first ICP (Inductively coupled plasma) tool at DTU Nanolab. It was manufactured by STS and is called the ASE (Advanced Silicon Etcher). Originally the main purpose of the ASE was etching of silicon using the Bosch process. However, after the acquisition of the DRIE-Pegasus and the retirement of our old RIE's the ASE will only serve as a "dirty" plasma etcher, etching silicon, Silicon oxide and silicon nitride on wafers with small amount of metals exposed and as a polymer etcher. The rule is that samples with up to 4 cm2 of metal on the surface will be allowed to process. Extra gasses was been added to the machine to allow SiO2 and SiN etching. Using these gasses may affect the conditioning of the chamber and thereby the stability of processes. Any clean processes and sensitive processes should take place in to the DRIEs or elsewhere.


In the case of the silicon etching on the ASE, an etch phase with SF6 and O2 alternates with a passivation phase with C4F8.

The user manual, quality control procedure and results, user APV(s), technical information and contact information can be found in LabManager:

Equipment info in LabManager

Process information

An overview of the performance of the ASE and some process related parameters

Purpose Dry etch of
  • Silicon
  • Thin layers of Silicon oxide and silicon nitride
  • Polymers such as polyimide, PDMS, PMMA, BCB and resists
Performance Etch rates
  • Silicon: ~0-15 µm/min (depending on features size and etch load)
  • Silicon oxide: <0.1 µm/min
  • Silicon nitride: <0.1 µm/min
Anisotropy
  • Good
Process parameter range Process pressure
  • ~0.1-95 mTorr
Gas flows
  • SF6: 0-600 sccm
  • O2: 0-99 sccm
  • C4F8: 0-300 sccm
  • Ar: 0-142 sccm
  • CF4: 0-99.9 sccm
  • CHF3: 0-99.9 sccm
  • H2: 0-40 sccm
  • He: 0-500 sccm
Substrates Batch size
  • 1 4" wafer per run
  • 1 2" wafer per run (requires carrier)
  • Or several smaller pieces on a carrier wafer
Substrate material allowed
  • Silicon wafers
    • with layers of silicon oxide or silicon (oxy)nitride
  • Quartz wafers
Possible masking material
  • Photoresist/e-beam resist
  • PolySilicon
  • Silicon oxide or silicon (oxy)nitride
  • Aluminium
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