Specific Process Knowledge/Etch/Etching of Silicon Oxide: Difference between revisions
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*[[Specific Process Knowledge/Etch/Wet Silicon Oxide Etch (BHF)|Wet Silicon Oxide Etch]] | *[[Specific Process Knowledge/Etch/Wet Silicon Oxide Etch (BHF)|Wet Silicon Oxide Etch]] | ||
*[[Specific_Process_Knowledge/Etch/III-V_RIE/III_V_RIE_ETCHES#CHF3.2FO2_etch |SiO2 etch using III-V RIE]] | *[[Specific_Process_Knowledge/Etch/III-V_RIE/III_V_RIE_ETCHES#CHF3.2FO2_etch |SiO2 etch using III-V RIE]] | ||
*[[/SiO2 etch using AOE|SiO2 etch using AOE]] | *[[/SiO2 etch using AOE|SiO2 etch using AOE]] | ||
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-4|SiO2 etch with DRIE Pegasus 4]] | |||
*[[/SiO2 etch using ASE|SiO2 etch using ASE]] | |||
*[[Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide|SiO2 etch using ICP metal]] | *[[Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide|SiO2 etch using ICP metal]] | ||
*[[Specific Process Knowledge/Etch/IBE⁄IBSD Ionfab 300|IBE/IBSD Ionfab 300]] | *[[Specific Process Knowledge/Etch/IBE⁄IBSD Ionfab 300|IBE/IBSD Ionfab 300]] | ||
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*Anisotropic etch: almost vertical sidewalls | *Anisotropic etch: almost vertical sidewalls | ||
*We prefer that SiO2 etch | *We prefer that SiO2 etch takes place in the AOE or Pegasus 4. | ||
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*Primarily for pure physical etch by sputtering with Ar-ions | *Primarily for pure physical etch by sputtering with Ar-ions | ||
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*Aluminium | *Aluminium | ||
*Chromium | *Chromium | ||
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*Any material that is accepted in the machine | *Any material that is accepted in the machine | ||
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*~75 nm/min (Thermal oxide) in BHF | *~75 nm/min (Thermal oxide) in BHF | ||
*~ | *~80 nm/min (Thermal oxide) in BOE 7:1 Etchant VLSI with Surfactant | ||
*~25 nm/min (Thermal oxide) in 5%HF | *~25 nm/min (Thermal oxide) in 5%HF | ||
*~6 nm/min (Thermal oxide) in 1%HF | |||
*~3-4µm/min in 40%HF | *~3-4µm/min in 40%HF | ||
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<br clear="all" /> | <br clear="all" /> | ||
==Dry etch with Hard mask== | |||
''By Martin Lind Ommen - ''fall 2016'' '' <br> | |||
Testing selectivities for SiO<sub>2</sub> etching with hard masks on AOE and ICP metal with different recipes.All tests are done with 100% etching load<br> | |||
[[File:Dry etching by Martin Lind Ommen Fall 2016.png|600px]]<br> | |||
MLO_psi is the version of SiO2_psi on labadviser that is shown under low line with reduction.<br> | |||
The recipe ICP is on ICP metal call: A SiO2 etch with C4F8 with resist mask<br> | |||
I had problems with this recipe - it gave polymer on the surface, therefor I do not have more info on that.<br> |
Latest revision as of 08:27, 22 August 2023
Unless anything else is stated, everything on this page, text and pictures are made by DTU Nanolab.
All links to Kemibrug (SDS) and Labmanager Including APV and QC requires login.
Feedback to this page: click here
Comparing silicon oxide etch methods at DTU Nanolab
There are a broad varity of silicon oxide etch methods at DTU Nanolab. The methodes are compared here to make it easier for you to compare and choose the one that suits your needs.
- SiO2 etch using III-V RIE
- SiO2 etch using AOE
- SiO2 etch with DRIE Pegasus 4
- SiO2 etch using ASE
- SiO2 etch using ICP metal
- IBE/IBSD Ionfab 300
- SiO2 etch using Plasma Asher (isotropic)
Compare the methods for Silicon Oxide etching
Wet Silicon Oxide etch (BHF/HF) | ASE | III-V RIE | AOE (Advanced Oxide Etch) | DRIE Pegasus 4 | ICP metal | IBE/IBSD Ionfab 300 | HF Vapour Phase Etch | |
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Generel description |
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Possible masking materials |
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Etch rate range |
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<500nm/min |
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Substrate size |
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Allowed materials |
In the dedicated bath:
In a plastic beaker:
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Dry etch with Hard mask
By Martin Lind Ommen - fall 2016
Testing selectivities for SiO2 etching with hard masks on AOE and ICP metal with different recipes.All tests are done with 100% etching load
MLO_psi is the version of SiO2_psi on labadviser that is shown under low line with reduction.
The recipe ICP is on ICP metal call: A SiO2 etch with C4F8 with resist mask
I had problems with this recipe - it gave polymer on the surface, therefor I do not have more info on that.