Specific Process Knowledge/Thermal Process/C3 Anneal-bond furnace: Difference between revisions

Latest revision as of 14:22, 31 January 2023

Feedback to this page: click here

This page is written by DTU Nanolab internal

Anneal-bond furnace (C3)

The Anneal-bond furnace (C3) is a Tempress horizontal furnace for oxidation and annealing of new and processed (e.g. bonded) silicon wafers. O₂) is used as an oxidant for dry oxidation, and for wet oxidation water vapour is being generated by a bubbler.

This furnace is the third tube in the furnace C-stack positioned in cleanroom B-1.

In this furnace it is allowed oxidize and anneal new wafers without doing an RCA clean first. Also silicon wafers from PECVD4 and wafers without any metal coming from PECVD3 and bonded wafers comming directly from the Wafer Bonder 02 (assuming they were clean and not have been exposed to any metal when entering wafer bonder) can be processed in the furnace without an RCA cleaning. Check the cross contamination information in LabManager before you use the furnace.

The user manual, technical information and contact information can be found in LabManager:

Anneal-bond Furnace (C3)

Process knowledge

Oxidation: look at the Oxidation page
Annealing: look at the Annealing page

Overview of the performance of the Anneal Bond furnace (C3) and some process related parameters

Purpose	Oxidation of Si wafers Annealing of processed wafers, eg. bonded wafers from EVG NIL	Annealing: Using N₂ Oxidation: Dry oxidation using O₂ Wet oxidation using H₂O vapour generated by a bubbler
Performance	Film thickness	Dry oxide:~ 0 nm to 300 nm (it takes too long to grow thicker dry oxide layers) Wet oxide: ~ 0 nm to 3 µm (23 hours wet oxidation at 1100 ^oC)
Process parameter range	Process temperature	800-1150 ^oC
	Process pressure	1 atm (no vacuum)
	Gas flows	N₂: 0-10 slm O₂: 0-10 slm
Substrates	Batch size	1-30 100 mm wafers (or 50 mm wafers)
Substrates	Substrate materials allowed	Silicon wafers Silicon wafers with layers of silicon oxide or silicon nitride Wafers from the LPCVD furnaces Wafers from PECVD4 Wafers from PECVD3 (without any metal) Wafers from Wafer Bonder 02 (assuming they were clean and not have been exposed to any metal when entering the Wafer Bonder 02)

@@ Line 1: / Line 1: @@
-==C3 Anneal-bond furnace==
+'''Feedback to this page''': '''[mailto:thinfilm@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.danchip.dtu.dk/index.php/Specific_Process_Knowledge/Thermal_Process/C3_Anneal-bond_furnace click here]'''
-[[Image:C3.JPG|thumb|300x300px|C3 Anneal-bond furnace. Positioned in cleanroom 2]]
-The C3 Anneal-bond furnace is a Tempress horizontal furnace for oxidation and annealing of (bonded) silicon wafers.
+''This page is written by DTU Nanolab  internal''
+[[Category: Equipment |Thermal C3]]
+[[Category: Thermal process|C3]]
+[[Category: Furnaces|C3]]
+==Anneal-bond furnace (C3)==
+[[Image:C3.JPG|thumb|300x300px|Anneal-bond furnace (C3). Positioned in cleanroom B-1/ Photo: DTU Nanolab internal]]
+The Anneal-bond furnace (C3) is a Tempress horizontal furnace for oxidation and annealing of new and processed (e.g. bonded) silicon wafers. O<sub>2</sub>) is used as an oxidant for dry oxidation, and for wet oxidation water vapour is being generated by a bubbler.
+This furnace is the third tube in the furnace C-stack positioned in cleanroom B-1.
+In this furnace it is allowed oxidize and anneal new wafers without doing an RCA clean first. Also silicon wafers from PECVD4 and wafers without any metal coming from PECVD3 and bonded wafers comming directly from the Wafer Bonder 02 (assuming they were clean and not have been exposed to any metal when entering wafer bonder) can be processed in the furnace without an RCA cleaning. Check the cross contamination information in LabManager before you use the furnace.
-This furnace is the third furnace tube in the furnace C-stack positioned in cleanroom 2. In this furnace it is allowed to enter wafers that come directly from bonding in the EVG NIL (assuming they were very clean when entering EVG NIL and not contain any metal). Check the [http://www.labmanager.danchip.dtu.dk/view_binary.php?fileId=1250 cross contamination chart].
 '''The user manual, technical information and contact information can be found in LabManager:'''
-'''[http://www.labmanager.danchip.dtu.dk/function.php?module=Machine&view=view&mach=89 Furnace C3: Anneal-bond]'''
+'''[http://www.labmanager.danchip.dtu.dk/function.php?module=Machine&view=view&mach=89 Anneal-bond Furnace (C3)]'''
 ==Process knowledge==
@@ Line 14: / Line 25: @@
 *Annealing: look at the [[Specific Process Knowledge/Thermal Process/Annealing|Annealing]] page
-==Overview of the performance of Anneal Bond furnace and some process related parameters==
-{| border="2" cellspacing="0" cellpadding="0"
+==Overview of the performance of the Anneal Bond furnace (C3) and some process related parameters==
+{| border="2" cellspacing="0" cellpadding="2"
 |-
 !style="background:silver; color:black;" align="center"|Purpose
-|style="background:LightGrey; color:black"|Oxidation and annealing
+|style="background:LightGrey; color:black"|
-|style="background:WhiteSmoke; color:black"|Oxidation:
+*Oxidation of Si wafers
-*Dry
+*Annealing of processed wafers, eg. bonded wafers from EVG NIL
-*Wet: with bubbler (water steam + N<sub>2</sub>)
+|style="background:WhiteSmoke; color:black"|
+Annealing:
+*Using N<sub>2</sub>
+Oxidation:
+*Dry oxidation using O<sub>2</sub>
+*Wet oxidation using H<sub>2</sub>O vapour generated by a bubbler
 |-
 !style="background:silver; color:black" align="center"|Performance
 |style="background:LightGrey; color:black"|Film thickness
 |style="background:WhiteSmoke; color:black"|
-*Dry SiO<sub>2</sub>: 50 Å  to ~2000 Å (takes too long to make it thicker)
+*Dry oxide:~ 0 nm  to 300 nm (it takes too long to grow thicker dry oxide layers)
-*Wet SiO<sub>2</sub>: 50 Å to ~5 µm (takes too long to make it thicker)
+*Wet oxide: ~ 0 nm to 3 µm (23 hours wet oxidation at 1100 <sup>o</sup>C)
 |-
 !style="background:silver; color:black" align="center" valign="center" rowspan="3"|Process parameter range
-|style="background:LightGrey; color:black"|Process Temperature
+|style="background:LightGrey; color:black"|Process temperature
 |style="background:WhiteSmoke; color:black"|
 *800-1150 <sup>o</sup>C
@@ Line 37: / Line 54: @@
 |style="background:LightGrey; color:black"|Process pressure
 |style="background:WhiteSmoke; color:black"|
-*1 atm
+*1 atm (no vacuum)
 |-
 |style="background:LightGrey; color:black"|Gas flows
 |style="background:WhiteSmoke; color:black"|
-*N<sub>2</sub>:5 sccm
+*N<sub>2</sub>: 0-10 slm
-*O<sub>2</sub>:5 sccm
+*O<sub>2</sub>: 0-10 slm
 |-
 !style="background:silver; color:black" align="center" valign="center" rowspan="2"|Substrates
 |style="background:LightGrey; color:black"|Batch size
 |style="background:WhiteSmoke; color:black"|
-*1-30 4" wafer (or 2" wafers) per run
+*1-30 100 mm wafers (or 50 mm wafers)
 |-
-|style="background:LightGrey; color:black"|Substrate material allowed
+|style="background:LightGrey; color:black"|Substrate materials allowed
 |style="background:WhiteSmoke; color:black"|
-*Silicon wafers (new from the box or RCA cleaned)
+*Silicon wafers
-*Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned)
+*Silicon wafers with layers of silicon oxide or silicon nitride
-*Quartz wafers (RCA cleaned)
+*Wafers from the LPCVD furnaces
-*From bonding in EVG NIL directly (assuming they fulfilled the above before entering the EVG NIL)
+*Wafers from PECVD4
+*Wafers from PECVD3 (without any metal)
+*Wafers from Wafer Bonder 02 (assuming they were clean and not have been exposed to any metal when entering the Wafer Bonder 02)
 |-
 |}