Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using ASE/tests CHF3+H2: Difference between revisions
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|colspan="5" style="text-align: center;" style="background: #efefef;" |'''Values''' | |colspan="5" style="text-align: center;" style="background: #efefef;" |'''Values''' | ||
|colspan="1" style="text-align: center;" style="background: #efefef;" |'''SEM pictures''' | |colspan="1" style="text-align: center;" style="background: #efefef;" |'''SEM pictures''' | ||
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|colspan="5" style="text-align: center;" style="background: #efefef;" |'''Values''' | |colspan="5" style="text-align: center;" style="background: #efefef;" |'''Values''' | ||
|colspan="1" style="text-align: center;" style="background: #efefef;" |'''SEM pictures''' | |colspan="1" style="text-align: center;" style="background: #efefef;" |'''SEM pictures''' | ||
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Revision as of 14:22, 22 April 2024
Tests performed with UV resist:
The tests were performed on a 100mm wafer patterned on MLA3, with 2.2um AZ5214E resist.
Tests performed with DUV resist:
The resist used was a negative DUV resist (UVN) with 915nm + 88nm BARC layer.
25 jan 2024 - SiO2 test
Etch test of Silicon Nitride
Tested on chips (2*2cm)