Specific Process Knowledge/Thermal Process/Oxidation/Breakdown voltage measurements
Feedback to this page: click here
Unless otherwise stated, this page is written by DTU Nanolab internal
Break-down voltage measurements
In order to evaluate the quality of the wet and dry oxide layers that can be grown in the oxidation furnaces, some break-down voltage measurement have been made.
The break-down voltage is the maximum voltage that can be applied to an insulating material like silicon oxide, before it starts to conduct.
The break-down voltage measurements were performed using an automated measure setup at DTU Health Tech. This setup automatically measures the break-down voltage in a pattern over each wafer. Each field in the pattern has a gold contact. The measurements are done by applying an increasing reverse voltage to each field in the pattern via a probe, until certain current that indicates a brea-kdown is reached, see the drawing.
Some fields in pattern are excluded from the results. The reason for this is either that the contact between the probe and the gold contact has not been been sufficient, or the probe has become dirty during the measurement - or simply to save some time.
The absolute break-down voltage has been measured, and the relative breakdown voltage has been calculated. The relative break-down voltage is the break-down voltage per nm of the oxide layer, i.e. the absolute break-down voltage divided by the oxide thickness
All the wafers have been made by DTU Nanolab, and the break-down voltage measurements have been made with help from Kitty Steenberg and Rune Sixten Grass from DTU Health Tech.
Procedure
The procedure for the breakdown voltage measurements is the following:
- RCA clean new 4" Si wafers (usually the cheapest SSP wafers used for furnace QC)
- Grow wet or dry oxide of both sides of the wafers in the oxidation furnace
- Oxidation recipe and temperature: Varies - See break-down voltage measurement results
- Oxidation time: Varies
- Annealing time: 20 min
- Spin resist on the front side of the wafers
- Remove the oxide on the back side of the wafers using BHF in Oxide etch 2
- Remove the resist on the front side of the wafers using plasma ashing (clean plasma asher)
- Deposit 10 nm Ti and 100 nm Au through a shadow mask on the front side of the wafers using e-beam deposition in the Temescal
- Measure the break-down voltage