Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-2/Nanoscale silicon etching with SF6 and O2

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Nanoscale silicon etching with SF6 and O2

This work was done by Vy Thi Hoang Nguyen @Nanolab in her ph.d. project ending 2020

The CORE sequence (meaning Clear, Oxidize, Remove and Etch) is a fluorocarbon-free directional plasma etch procedure that enables a higher selectivity, creates pattern independence of etching profiles and works excellent at room temperature. The CORE process resembles the well-known SF₆-based Bosch process, but the usual C₄F₈ inhibitor is replaced by O₂ oxidation with self-limiting characteristics. Therefore the CORE result is similar to Bosch, however has the advantage of preventing the pile-up of fluorocarbon deposits at the topside of deep-etched or nano-sized features. At the same time, process drift is minimized as the reactor wall is staying perfectly clean. The CORE process has shown an excellent performance in high aspect ratio (3D) nanoscale structures with an accurate and controllable etch rate between 1 and 50 nm min⁻¹ (and SiO₂-selectivity of ca. 35) using the etch-tool in the RIE-mode. By adding the ICP source (DRIE-mode), a directional etch rate up to 1 μm min⁻¹ (at 50 sccm SF₆ flow) and selectivity >200 for SiO₂ is possible.

CORE uses a sequence of SF₆ plasma to etch silicon (the E-step), repeatedly alternated with O₂ plasma to passivate the sidewall of the etching features (the O-step). Both steps have a very low bias in order to minimize the mask erosion. The R-step is included after the O-step to remove the passivation layer from the horizontal surfaces completely, but leaving the vertical wall passivation intact. This step operates at a very low pressure to create a high plasma potential that will combine with the DC self-bias to enhance the ion energy for the directional removal. The C-step is less evident, but it is added as a purge step to remove the SF6 species from the reactor before the O-radicals from the next O-step arrive.

The CORE recipe is shown as below

The CORE cycle design rules and optimized recipe for the etch rate fixed at 15 nm\min

Rule 1: 2 min E-time needs 2 s O-time. Every 2 min extra E-time will need 1 s extra O-time until a maximum of 14 min E-time.

Rule 2: Every second of O-time needs at least 3 s R-time (for 8 min E-time).

Rule 3: The undercut is roughly half of the gained etch depth per CORE cycle.

Silicon wafers are prepared with 1.5 μm thick resist patterns (AZ MIR 701 DUV resist from MicroChemicals) and exposed using a maskless aligner (MLA150, Heidelberg) to create patterns above 400 nm.

For nanosized patterns between 30 and 100 nm, an electron beam writing system (JEOL JBX-9500FSZ) is used with positive tone e-beam resist ZEP520A (ZEON).

Below are some SEM images of the silicon nanostructures achieved by the CORE process:

Submicron silicon trenches and lines derived from the fine-tuned CORE sequence.

Submicron silicon holes derived from the fine-tuned CORE sequence. The side wall angle is ca. 2°.

Submicron silicon pillars derived from the fine-tuned CORE sequence.

Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.

For more details, please contact Henri Jansen (henrija@dtu.dk) or Vy Thi Hoang Nguyen (vthongu@dtu.dk).