Introduction

The JEOL 9500 E-beam writer offers world class performance this however comes at a price of a fairly steep learning curve. This page is specifically intended to guide new users through their very first exposure on the system. In this guide we will set up a simple wafer/chip exposure. The complexity is kept at a relatively low level and we encourage new users to make sure their first job (first training session) matches this complexity level. More complex jobs can be run when a user is more familiar with the system.

Training on the JEOL 9500 system can be requested by sending a mail to e-beam@nanolab.dtu.dk. Please attach a process flow and any other relevant information for your process. Be advised that the booking calendar on the JEOL 9500 system is always very full, typically a user can expect the first training session about four weeks after the initial request.

General workflow

The general workflow of E-beam lithography on the JEOL 9500 system is somewhat similar to that of UV lithography with a few added steps. The general workflow is

Resist coating and baking
Application of discharge layer on substrates with >100 nm non-conducting films
Pattern preparation, possibly including Proximity Effect Correction
Jobdeck file (JDF) and schedule file (SDF) preparation
Job file compilation
Job file verification
Sample mounting
Cassette transfer
System calibration
Exposure
Cassette and sample unloading
Discharge layer removal
Development

In the following we will look at each step in more detail and show step by step how to make a wafer/chip exposure.

Resist coating

DTU Nanolab offers a few different standard resist as given in the table below. Typically layers of 50-500 nm are applied. The Gamma UV & E-beam coater has predefined recipes for various thickness of CSAR resist. For other thickness or other resist the more manual Lab Spin 2 or 3 coasters can be used. If using the Lab Spin coaters please refer to the table below for information on thickness versus spin speed and soft bake temperature and baking time suggestions.

Table with: Resist, polarity, process guideline link, spin speed, baking info, developing agent, removing agent

For our example process we will use a standard 4” silicon wafer and coat it with 250 nm CSAR on the fully automatic Gamma E-beam & UV coater using recipe xxxx.

DTU Nanolab provides the following standard EBL resists.

Resist	Polarity	Manufacturer guidelines	Spin Coater	Thinner	Developer	Rinse	Remover	Polynomial
CSAR 62 / AR-P 6200.09	Positive	CSAR 6200 info	Spin Coater: Gamma e-beam & UV or Spin Coater: Labspin 02/03	Anisole	AR-600-546, AR-600-548, N50, MIBK:IPA	IPA	AR-600-71, 1165 Remover	a = 7252.2, b = -0.454
AR-N 8200	Negative	AllResist	Spin Coater: Labspin 02/03		AR 300-47	DIW
AR-N 7520	Negative	AR-N7500-7520.pdf‎	Spin Coater: Labspin 02/03	PGMEA	AR 300-47	DIW

Resist thickness as function of spin speed on Lab Spin 2/3 can be estimated from the parameters above as y = ax^b, where y is resist thickness in nm and x is spin speed in RPM.

Discharge layer application Electron beam exposure of non-conductive substrates will lead to a rapid and local build up of electrons and hence a build up of charge that will deflect the incident beam and distort the pattern writing. Non-conductive substrates can be coated with a metal film to provide sufficient conductance. A typical way to do this is to apply a 20 nm thermally evaporated Al layer on top of the resist layer. Please do not apply metals from e-beam evaporation sources as this process will to some extend exposure the resist with electrons from the metal evaporation process. Al is preferred due to its low atomic mass and hence minimum amount of forward beam scattering and also since it is very easy to etch away after e-beam exposure.

Since we are using a regular silicon wafer in our example job we will not need to apply a discharge layer.

Pattern preparation Users will typically have their pattern in either CIF or GDS format. The JEOL 9500 system can only expose patterns defined in the v30 format and thus as a minimum the pattern must be translated to v30. This can be done with Beamer from Genisys. In this example job we will also show how to apply a Proximity Effect Correction (PEC) to the pattern, this is also done in Beamer.

PEC is a complex topic and we shall only touch upon it lightly in this guide. The need for PEC arises from the fact that the high energy incident electrons to some extend will back scatter from the sample or cause secondary electrons from the sample to interact with the resist and cause a secondary exposure of the resist. On a silicon substrate this secondary exposure can lead to exposure of the resist up to 30 µm away from the incident beam. Due to this areas with dense patterns will receive a relative high secondary exposure compared to sparse patterns and thus a higher total dose. To mitigate this a Proximity Effect Correction is applied to intentionally reduce the dose on dense patterns and ensure all pattern elements receive the same dose.

In order to prepare your .v30 file you must have access to Beamer. It is available on the support PC in the EBL control room as well as on a computer in room xxx of building 347. Users should always make the necessary PEC and file conversion well ahead of their booked slot on the JEOL 9500 system.

Jobs in Beamer are setup in a node based manner. We start with an import node that simply imports your CIF/GDS file into Beamer. Once a node is setup you must press the arrow in the node to execute it. The result can be seen in the viewer. Verify visually that your design appears to be imported correctly.

In this case our GDS file contains multiple layers and thus we need to extract the particular layer needed for exposure. We will use an extract node to extract that particular layer.

As our design consist of both dense and sparse aras we will apply a Proximity Effect Correction by adding a PEC node. The setup of the PEC node can be somewhat overwhelming as it has many options and settings which are beyond the scope of this guide. We will keep it simple and use a template from the local archive. The closest match to our sample in the archive is the Si substrate with 200 nm PMMA resist. After execution of the PEC node our design has been broken into xx different dose classes. To see the dose modulated design you need to turn on “dose view” and show the dose table in the tree of the viewer. In this case we can see that our design has been assigned dose modulations between x.xx and x.xx. A dose modulation of 1.3 means that these elements will receive 1.3 times the base dose, i.e. a dose increase of 30% from the base dose (that we have yet to define).

As a final step in Beamer we will export the design to .v30 using an “Export” node. This node also has many options for particular ways to choose writing order, writing field sizing and many other parameters that goes beyond the scope of this guide. The only thing we will do is to change the machine type from the default “FS 9300” to “FS 9500” since our system is the 9500 and choose the location to save to output to. After execution the .v30 file is saved to your selected location. Along with it will also appear a .JDI file. This is a text file that contains the dose modulation table, this is needed in the next step where we will setup the job files.

You can find a video demonstration of the procedure right here [link].

SDF and JDF file preparation In order to execute the pattern writing a significant number of parameters must be defined for the job. These are defined in two text files; the Schedule Definition File (SDF) and Jobdeck Definition File (JDF). The system has a close to zero tolerance on syntax error from the user and thus these files should be prepared carefully, usually by using templates and correcting the parameters to suit your exposure. We encourage users to download and use SuperEdi for editing SDJ/JDF files. As the JEOL 9500 is operated from a Unix computer you must save your SDF/files in Unix format, available as a option from the “Save As” menu in SuperEdi.

For our example job we will use the following files.

!SDF and JDF file content with line numbers!

Description of commands.

Much more information on various commands in SDF/JDF files are available in the SDF and JDF file manual. [link]

Job file compilation At this stage we have a v30 file containing the pattern data and an SDF and JDF file describing the exposure parameters. These must be compiled into a magazine file (.mgn) which will completely define the exposure job.

Magazine files are compiled directly on the control computer and hence the v30, SDF and JDF files have to be transferred to this computer using the FFTP client available on the support PC. For first time use FFTP has to be setup on your account on the support PC.

Login to the support PC using your DTU credentials. Open “FFTP” Click “New connection” Write “9500new” in the naming field Fill in the control computer IP address 10.54.?.? in the “?” field In the destination field add the control computer job file library path “eb0/job/danchip/??”

FFTP supports drag and drop of files, not only between its own two windows but also to Windows Explore windows.

With FFTP correctly setup, connect and move your SDF and JDF files to [path]. Move the v30 file to [path]

Once the files are transferred to the EBL control computer we can compile the files into a magazine file. The Unix interface has several desktops. Desktop one is used for EBL control and desktop two is used for file compilation. Switch to desktop two, select the terminal window and write “schd -exptime sdffilename”.

If compilation is successful the terminal will provide a table of exposure sequences and their corresponding exposure times. Also, a .mgn file will be generated in the same folder as the SDF file.

If compilation does not succeed the terminal will respond with a number of errors indicating which line(s) of the SDF or JDF file is causing the error.

Job file verification To ensure that the pattern and exposure parameters are correct one should always do a brief verification of the content of the .mgn file. From the right hand side of desktop two click on the “ACHECK” tool. From the window opening up choose “File” -> “Open” and open your magazine file.

Sample mounting The JEOL 9500 system uses a proprietary sample cassette format and thus each sample must be mounted in an appropriate cassette. Cassettes are available for wafer sizes from 2” to 8”. Smaller chips must be mounted in dedicated chip cassettes with slots of four different sizes available. Slots are all 50 mm in width, the heights are 20, 12, 8 or 4 mm. A chip must have one side length at least 1 mm larger than the height such that it can safely be clamped in the slot. Thus the smallest possible chip to expose must have one side length of at least 5 mm.

The system is fitted with an auto stocker system that can store 10 cassettes. It is thus possible to prepare multiple substrates and define an automated job to execute exposure of several substrates across several cassettes.

Examples of cassettes are seen below. [Insert images]

For our exposure we will use a 4” cassette. The procedure is best illustrated with a video [link].

Users are allowed to unload a cassette from the auto stocker system and mount their sample(s). Users are however not allowed to put cassettes back into the auto stocker system and thus users must always contact the Nanolab E-beam loading team prior to exposure to have their cassette loaded into the auto loading system. The E-beam loading team can be contacted at [email]. Upon loading a cassette Nanolab staff will visually verify the sample has been inserted and secured correctly. Incorrect sample mounting can lead to severe damage to the internal parts of the JEOL 9500 exposure system.

- - Any user found to violate this rule will be permanently excluded from using the JEOL 9500 system.***

Cassette transfer Prior to exposure the chosen cassette has to be transferred from the auto stocker system and to the main chamber. This is done from the “Loader” module on the control computer

System calibration After cassette transfer the system has to be calibrated with the chosen beam current profile. This is done in a mostly automated sequence with only minute input from the user.

Discharge layer removal After exposure the discharge layer must be removed. In the case of thermal Al this is conveniently done using MIF 726, the UV developing agent found on both the “Gamma TMAH UV developer” and “TMAH manual developer” tools. The etch rate of thermal Al in MIF 726 is 30 nm/min. For etching a standard 20 nm thermal Al layer we recommend to choose a 60 s developer cycle on either tool.

Development Development of EBL resist can be done in two ways, either in beakers or on the automatic E-beam developer tool. The latter is equipped with ZED N50 for development of ZEP resist and AR 600-546 for development of CSAR. The system can handle chips or wafers up to 6”. It has predefined develop cycle times of 15, 30, 60 and 120 seconds.

For other developers users have to use the EBL development fumehood in E4 and manually develop their substrates in beakers of appropriate size. Please observe there are beakers dedicated solvent developers such as isopropanol and other beakers dedicated alkaline developers such as ??.

Please refer to our suggested development parameters in the table below. [table of development]