Specific Process Knowledge/Etch/Etching of Bulk Glass/HF Etch of Glass

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Wet HF-etch of bulk glass: fused silica vs. borofloat

	Fused silica	Borofloat glass
General description	40% pre-mixed HF	40% pre-mixed HF
Possible masking materials	LPCVD silicon (good adhesion and step coverage) PECVD silicon (less good step coverage and low deposition rate)	Sputtered silicon (Alcatel) (bad adhesion and step coverage) Sputtered silicon (Lesker) (good adhesion at elevated temperature)
Etch rate	~700 nm/min (patterned silica, slow stirring) ~800 nm/min (non-patterned silica, slow stirring)	~3.9 µm/min
Uniformity	~ 2% (slow stirring, horizontal wafer)
Batch size	1 wafers at a time	1 wafer at a time
Size of substrate	4" wafers	4" wafers
Allowed materials	No restrictions	No restrictions

Deep Glass Etch Challenge

Here are some notes made by bghe@Nanolab in Dec. 2010, about how to do deep wet etching in glass. These notes are based on some literature studies, some experiments done here at Nanolab and some asking around.

The challenge is to a find good masking materials for glass etch to obtain a deep glass etch without pinholes.

Parameters that influence

The wet etch (what chemical/concentration to choose)
The glass type (and pretreatment): fused silica, borofloat, Pyrex, other glasses
Masking material

The wet etch (what chemical/concentration to choose)

The chemical for glass etch is HF - no other chemicals etches glass in a rate that is relevant for deep glass etch. Therefor the question in this section is what concentration to use for deep etch.

Buffer and 5% HF: etch rate too slow for a deep etch since it is hard to find a mask that lasts so long
40% HF: Fast glass etch - and we have it on the shelf
49% HF: Faster glass etch - gives better selectivity to mask - but we do not have it on the shelf and it is even nastier to work with than 40% HF.

The glass type (and pretreatment)

There are many types of glass from pure SiO2 as quartz and fused silica to glasses with different levels of other oxides than SiO2. These are typically[1,2]: B2O3, Na2O, K2O, Al2O3, ZnO, TiO2, CaO, MgO and traces of others. Pure SiO2 etches much slower than glasses with contents of some of these oxides. Others of these oxides are insoluble in HF (CaO, MgO and Al2O3) and are the course of the glass surface being very rough after the HF etch [1]. In some cases the etch rate decreases during the etch due to these insoluble oxides and can go to nearly zero. The etch rate of a Pyrex compared to quartz is typically 5-10 times faster. It is possible to get glasses that etch 30 times faster than quartz [2].

If you need to do a deep etch in glass and you do not need pure SiO2 as quartz or fused silica you should consider using a glass with some of the other oxides. This will improve the selectivity to you masking material. But be aware that there are much equipment in the Danchip clean room where processing on these "non clean" glasses are not allowed.

Pretreatment: For some glasses annealing before etch can improve the etch rate with a factor or ~2. This has been shown for Corning 7740 annealed at 560 degrees[1]

Masking materials

Masking materials I have considered are:

Photoresist
Cr/photoresist
PolySi
Cr/Au

Here is a small table of potential problems with these masking material and some suggestions to how to over come them.

Masking material	Potential problems	Possible solution
Photoresist	Delaminates after few min. in HF	Use Cr as adhesion layer (*kbm) and bake photoresist at 120degrees ½h
Cr/Photoresist tested by kbm*	Probably some pinholes and limited life time	Works well for microchannels etched down to 20µm
Polysi	Problems with adhesion to glass pinholes/rough edges	Deposit Si at elevated temperatures (200 dg) Leave photoresist on - bake at 120 degrees ½h
Cr/Au	Pinholes/rough edges	Leave photoresist on - bake it at 120 degrees ½h

*kbm is Klaus Bo Mogensen from Nanotech: klmo@nanotech.dtu.dk

Some experimental results

Cr/Photoresist as masking material

Has been tested by Klaus Bo Mogensen from Nanotech: klmo@nanotech.dtu.dk

Klaus has used 200-300nm Cr and 4µm Photoreist to mask a borofloat glass for etchning microchannels in a depths down to 20µm. The photoresist was baked at 120 degrees. The etch was done in 40% HF.

It worked very well. Klaus expects the mask to last even longer if needed. There might have been some pinholes but a few pinholes are not a problem when making micro channels.

PolySi as masking material

This project was started up due to problems with adhesion of Si sputtered on Pyrex using the Alcatel sputter and e-beam deposition system. In the past this procedure has been used with some success using sputtered silicon from the Alcatel (but there has been problems with adhesion of the Si):

Piranha clean
Bake-out at 250 ^oC (>2.5 hours)
Plasma ashing
Sputter-deposit in Alcatel: Power: 550W, Ar-pressure: 10 $^{-2}$ mbar (base pressure: 10 $^{-6}$ mbar)
Patterning of the silicon using either wet (poly-etch) or dry etching

From the literature we found the advise that the deposition should take place at elevated temperatures to make Si adhere to glass. We do not have that possibility in the Alcatel system there for we tried with the Sputter System Lesker. The result was that the adhesion was OK when deposition took place at 200 degrees and the etch was done in 40% HF. There was however severe problems with pinholes and rough edges. After more literature studies I tried leaving on the photoresist (used for pattering the polySi) and baked it at 120 degrees. That helped but a few pinholes could still be found.

Figure 1 15min HF 40% etch of borofloat with ~250nm Si mask made in the Sputter System Lesker at 200dg. Resist for masking the Si has been removed before the etch. Rough edges and many pinholes were see after the etch.

Figure 2 15min HF 40% etch of borofloat with ~500nm Si mask made in the Sputter System Lesker at 200dg. Resist for masking the Si has been left on and baked at 120 degrees.No rough edges and only few pinholes were see after the etch.

Conclusion for using Si as masking layer: Si deposited in the Sputter System Lesker at 200 degrees can be used as masking material but there will be some pinholes.

Deposit at 200 degrees: To avoid adhesion problems.
Leave the photoresist (from the pattering of the silicon) on and bake it at 120 degrees before the the HF etch. This reduces the number of pinholes.
Time consuming: It takes almost a whole day to do the layer in the Sputter System Lesker at elevated temperature. Due to the sensitive loading arm (this arm has been changed /bghe 2017-02-02) in the Lesker system you need to enter your sample before turning op the temperature to 200 degrees and after the deposition the chamber needs to cool down again before you can remove your sample. This is a major draw back and is a reason for trying to find alternative masking materials.
Amorph Si will probably work better and give less pinholes. Here at Danchip this can only be made on quartz/fused silica since other glasses are not allowed in furnace for deposition of amorph silicon (B4) nor in the PECVD3.

Cr/Au as masking material

Gold should in principal be a good masking material for glass etch in HF as gold is not being etched by HF. Gold do not adhere very well to glass therefor a thin layer of Chromium is deposited between the glass and the gold. Chromium adhere good to both glass and gold. The Chromium and the Gold has been deposited in the Alcatel E-beam evaporator. From the literature I found recommendation to also leave the photoresist on the gold and bake it to avoid/reduce pinholes.

Figure 3 15min HF 40% etch of borofloat with 50nm Cr 400nm Au mask made in Alcatel E-beam evaporator. Resist for masking the Cr/Au etch has been left on and baked at 120 degrees for ½ hour before the HF etch. These images have been taken at random places on the wafer. They illustrate the low number of pinholes.

Figure 4 15min HF 40% etch of borofloat with 50nm Cr 400nm Au mask made in Alcatel E-beam evaporator. Resist for masking the Cr/Au etch has been left on and baked at 120 degrees for ½ hour before the HF etch. These images have been taken where I found some pinholes on the wafer. They illustrate that the surface is not pinhole free.

Conclusion for using Cr/Au as masking material: Cr/Au can be used as masking material for deep glass etch but some pinholes will be made even when keeping the resist on and bake it.

Remember the Cr as adhesive layer
Keep the resist on (from the pattering of Cr/Au layer) and bake it at 120 degrees for ½ hour.
Draw back: some pinholes are created - problem becomes worse with longer etching time in HF. This is an expensive masking material due to the thick Au layer.

Why pinholes and rough edges and why does baked resist help?

PolySi: When making polycrystalline silicon there is a chance that there will be cracks/holes between the crystals where the HF can enter and reach the glass surface. When spinning photoresist on top of the PolySi surface the resist will enter the cracks/holes and cover the surface. When etching in the HF the resist on the surface will delaminate within some minutes but the resist inside the cracks/holes will last much longer.

Au: Defects in the Au layer can result in cracks/holes due to film stress. These cracks will be created when the sample comes to normal atmospheric pressure and temperature and then HF can enter and reach the glass surface. When spinning photoresist on top of the Au surface the resist will enter the cracks/holes and cover the surface. When etching in the HF the resist on the surface will delaminate within some minutes but the resist inside the cracks/holes will last much longer especially if the resist is hard baked[1]. It might also be a possibility to reduce pinholes by making multiple layer of Au [1] but it has not been tested here.

How to reduce surface roughness

Glasses that contain oxides that are insoluble in HF, like CaO, MgO and Al2O3 will get very rough surfaces when etched in HF[1]. The roughness of the surface can be reduced by adding HCl to the HF. The optimal ratio depend on the content of the glass (e.g. HF:HCl 10:1 for Corning 7740 [1]).

References

C. Iliescu et al., Sensors and Actuators A 133 (2007) 395-400
H. Zhu et al., J. Micromech. Microeng. 19 (2009)065013 (8pp)