Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using ASE

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Development work: SiO2 etch with resist mask, sample on carrier (Si carrier)

Our old RIE systems have to the end of their lives been used a lot for etching samples that could not be clamped/cooled in the ICP systems. The higher plasma density in the ICP's make their processes more tough on resist masks, probably because of too much heating. Therefor the ICP's are using cooled bottom electrodes with He back side cooling to keep the temperature low for the resist mask to survive. When decommissioning the RIE's (RIE1 and RIE2) a need came for developing recipes on the ICP's that could etch Si, SiO2 and SiN without clamping/cooling the substrates. This part consideres eting in SIO2. First an attempt to run the ASE in RIE mode using only the platen generator was made. This resulted in not so nice sidewalls due to redeposition and low etches, see below. After that the development focused on running with both low coil power and low platen power.

SiO2 etch with resist mask, sample on carrier (Si carrier) in the RIE mode using CF4/CHF3/H2 chemistry

By Berit Herstrøm @danchip, January-Marts 2018

In this studie a design of experiments (DOE) were done in RIE mode, meaning using only the platen power and avoiding the coil power. This was to keep the temperature of the substrate low without helium back side cooling the sample.

Results for the DOE

• Redeposition File:REdeposition ASE_SiO2_RIE_01_design + results - Fit Least Squares.pdf
• Etch rate File:Etch rate ASE_SiO2_RIE_01_design + results - Fit Least Squares.pdf

Conclusion

The conclusion of this work was that using that platen power alone was giving too much re-deposition on the sidewalls leading to very rough sidewalls. To reduce/avoid it the platen power had to be lowered so much that the etch rate got unacceptably low. There for next study included the coil power.

SiO2 etch with resist mask, sample on carrier (Si carrier) in the ICP mode using C4F8/H2 chemistry

By Berit Herstrøm @danchip, January-Marts 2018

The challenge was to develop a SiO2 etching recipe that can be used for samples on a carrier. Samples that cannot be clamped and cooled. The goal was to keep a good selectivity to the resist mask and get a vertical sidewall, without getting a lot of redeposition on the sidewalls. The testing regime was using both the coil power and the platen power with C4F8/H2 chemistry.

Take a look at development flow and the results here: Media:ASE SiO2 etch on carrier ICP C4F8 H2 no He rev02.pdf . Zoom in to read and see the images: (Ctrl + "+")

Effect chart made from the observations in this studie

Effect chart of increasing input factors	Etch rate	Selectivity to resist	Sidewall	Other Observations
Coil power ↑	↑	↓		At high coil powers the sample surface gets so hot that it affects the resists too much. The resist changes form at the high powers and the plasma/ions breaks through the resist at different rates, leaving the SiO2 surface very rough. 150W seems to be good for etching about 1 µm of SiO2. Remember this is for samples that are NOT clamped and cooled.
Platen power ↑	↑	↓		High Platen power also makes the sample surface too hot so it affects the resist in a bad way. Keeping it very low when the coil power is also kept low gives a very low etch rate. At least up to 25 W seems OK, with coil power 150W
Total flow rate ↑	↓	↑		We are here in the pumping rate limited regime where the etch rate goes down with the flow rate. But at the same time the selectivity goes up because the residence times gets shorter. This probably leads to CF2/F increasing and should improve the selectivity.
H2/C4F8 ↑	↓	↑		H/F increasing also increases the selectivity. H reacts with F to form HF and this makes the F/C decrease giving higher selectivity. Too must H2 gives too much polymer formation and this will stop the etch completely, so it is a matter of finding a balance. Even before the polymer deposition get so high that it stops the etch it still produces so much deposition on the sidewalls that it affects the etch profile, take a look at number 15, 18 and 25 in the development flow:Media:ASE SiO2 etch on carrier ICP C4F8 H2 no He rev02.pdf. The critical dimension changes (line width increases), the sidewalls get rounded but it can prevent trenching.

The recommended recipe for SiO2 etch using a carrier is this

Parameter	Recipe name: 1SiO2_02	Recipe name: 1SiO2_xx
Coil Power [W]	150	100
Platen Power [W]	25	25
Platen temperature [oC]	20	20
C4F8 flow [sccm]	36	10
H2 flow [sccm]	13	10
He flow [sccm]	0	100
Pressure [mTorr]	2.5	2.5

Results for 1SiO2_02 on a piece of wafer on a Si carrier

Material to be etched	Etch rate using SiO2_res
Etch rate in SiO2	22.1 nm/min
Etch rate in resist (MIR)	12.5 nm/min
Selectivity (SiO2:resist)	1.8
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