Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using ASE
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Revision as of 13:30, 5 April 2018 by Bghe (talk | contribs) (→Development work: SiO2 etch with resist mask, sample on carrier (Si carrier))
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Development work: SiO2 etch with resist mask, sample on carrier (Si carrier)
By Berit Herstrøm @danchip, January-Marts 2018
The challenge was to develop a SiO2 etching recipe that can be used for samples on a carrier. Samples that cannot be clamped and cooled. The goal was to keep a good selectivity to the resist mask and get a vertical sidewall, without getting a lot of redeposition on the sidewalls. The testing regime was using both the coil power and the platen power with C4F8/H2 chemistry.
Take a look at development flow and the results here: Media:ASE SiO2 etch on carrier ICP C4F8 H2 no He rev02.pdf . Zoom in to read and see the images: (Ctrl + "+")