Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE/Standard recipe with resist mask/Striation
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Striation: Side wall roughness
When etching silicon oxide rough sidewalls are most often seem. This effect is called striation, because it creates stripes along the etched profile. The literature gives several explanations for this. The two main courses seems to be:
- deposition on the sidewalls as the etch proceeds, coursing masking effects
- This can come from flour-carbon polymers from the plasma (some this this layer protects from striation)
- Re-deposition of sputtered SiO2
- damage of the resist mask coursed by plasma heating and/or interaction with the resist. This pattern change at the edge gets transferred to the oxide profile during the etch.
- Resist edge gets rough during etching due to plasma heating (out-gassing while the surface get UV hardened. This make the resist crumple).
- The edge can maybe also get roughened due to sputtering.
This work is focused on trying to improve the resist to avoid the resist damage during etching. From a previous test it has been seen that pre baking the resist AZ1452e at 150 degrees for 5 min can prevent the crumpling of the resist, See results HERE. However this makes the resist flow so the edge profile will not remain vertical.
- First the out present three standard resists (AZ5214E, AZ nLof and AZ Mir) were characterized after and SiO2 etch in the AOE (recipe: SiO2_mres)
Sidewall roughness and resist surface after etch viewed with SEM
- Striation with different resists used
Roughness of the resist after etch measured with the AFM