Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE/PolySi mask
High etch rate recipe
| Parameter | Recipe name: SiO2_psi (SiO2 etch with pSi mask) |
|---|---|
| Coil Power [W] | 1300 |
| Platen Power [W] | 500 |
| Platen temperature [oC] | 60 |
| He flow [sccm] | 300 |
| C4F8 flow [sccm] | 18 |
| H2 flow [sccm] | 0 |
| Pressure [mTorr] | 4 |
| Typical results | PolySi mask - tested by Yunhong Ding @fotonik | PolySi mask - tested Feb. 2012 by bge@danchip |
|---|---|---|
| Etch rate | ~0.55 µm/min | 0.50 µm/min |
| Selectivity | 1:~10 | 1:17 |
| SiO2 etch uniformity | not tested | ±4.5% over a 100mm wafer |
| Profile [o] | not tested | see images |
| Images | . | See here |
| Comments | . | Line width reduction is about 2.5µm when etching 12.5µm down. See the images to get more info on this |
Low line width reduction recipe
It is difficult to get very low line width reduction using P-Si as masiking material. This is due to the fact that the etch gas C4F8 that is used to etch SiO2 also etches Si very well. The best result so fare is given here:
| Parameter | Poly Si mask |
|---|---|
| Coil Power [W] | 1100 |
| Platen Power [W] | 170 |
| Platen temperature [oC] | 50 |
| He flow [sccm] | 450 |
| C4F8 flow [sccm] | 12 |
| H2 flow [sccm] | 0 |
| Pressure [mTorr] | 6 |
| Spacer settings [mm] | 100 |
| Typical results | PolySi mask - tested spring. 2012 by bge@danchip |
|---|---|
| Etch rate | ~0.25 µm/min |
| Selectivity | 1:12 |
| SiO2 etch uniformity | ±1.1% over a 100mm wafer |
| Profile [o] | see images |
| Images | See here |
| Comments | Line width reduction is about 1µm when etching 7.5µm down. See the images to get more info on this |