Specific Process Knowledge/Etch/ASE (Advanced Silicon Etch)

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The ASE

The ICP-DRIE tool at Danchip: STS ASE - positioned in cleanroom2

The ICP-DRIE (Inductively Coupled Plasma - Deep Reactive Ion Etcher) tool at Danchip is manufactured by STS and is called the ASE (Advanced Silicon Etcher). The main purpose of the ASE is etching of silicon using Bosch process.

The Bosch process: Etching of silicon

The Bosch process uses alternation between an etch cycle and a passivation cycle. Introducing a passivation step in an etch process is very beneficial for the control of the angle of the sidewalls in the etch process because it allows us to cover them with a protective layer that suppresses the isotropic etching. Combined with the high plasma density in the ICP chamber, the excellent sidewall control enables us to etch high aspect ratio structures in silicon with very high etch rates.

In the case of the silicon etching on the ASE, an etch phase with SF6 and O2 alternates with a passivation phase with C4F8.


A rough overview of the performance of the RIE´s and some process related parameters

Purpose Dry etch of
  • Silicon
  • Silicon oxide
  • Silicon (oxy)nitride
Performance Etch rates
  • Silicon: ~0.04-0.8 µm/min
  • Silicon oxide:~0.02-0.15 µm/min
  • Silicon (oxy)nitride:~0.02-? µm/min
. Anisotropy
  • Can vary from isotropic to anisotropic with vertical sidewalls and on to a physical etch were the sidewalls are angled but without etching under the mask.
Process parameter range Process pressure
  • ~20-200 mTorr
. Gas flows
  • SF: 0-130 sccm
  • O: 0-100 sccm
  • CHF: 0-100 sccm
  • CF: 0-84 sccm
  • H: ?sccm
  • Ar: 0-145 sccm
  • N: 0-100 sccm
  • CF: 0-24 sccm
Substrates Batch size
  • 1 4" wafer per run
  • 1 2" wafer per run
  • Or several smaller pieces
. Substrate material allowed
  • Silicon wafers
    • with layers of silicon oxide or silicon (oxy)nitride
  • Quartz wafers
. Possible masking material
  • Photoresist/e-beam resist
  • Silicon/PolySi
  • Silicon oxide or silicon (oxy)nitride
  • Aluminium
  • Other metals if the coverage is <5% of the wafer area (ONLY PECVD3!)