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Specific Process Knowledge/Thin film deposition/Furnace LPCVD PolySilicon: Difference between revisions

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*Amorphous polySi: 0-1000 nm
*Amorphous polySi: 0-1000 nm
*Boron doped polySi: 0-1000 nm
*Boron doped polySi: 0-1000 nm
4" furnace
4" furnace:
*Standard polySi: 0-2000 nm
*Standard polySi: 0-2000 nm
*Amorphous polySi: 0-2000 nm
*Amorphous polySi: 0-2000 nm
*Boron doped polySi: 0-2000 nm
*Boron doped polySi: 0-2000 nm
*Phosphorus doped polySi: 0-1000 nm
*Phosphorus doped polySi: 0-1000 nm
Thicker layers have to be deposited over more runs
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|style="background:LightGrey; color:black"|Step coverage
|style="background:LightGrey; color:black"|Step coverage
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*Good
*Good
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|style="background:LightGrey; color:black"|Thickness uniformity
|style="background:LightGrey; color:black"|Film quality
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*Good
*Deposition on both sides of the substrate
*Good uniformity over the wafer
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!style="background:silver; color:black" align="left" valign="top" rowspan="3"|Process parameter range
!style="background:silver; color:black" align="left" valign="top" rowspan="3"|Process parameter range
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*Amorphous polySi: 560-580 <sup>o</sup>C
*Amorphous polySi: 560-580 <sup>o</sup>C
*Boron doped polySi: 600-620 <sup>o</sup>C
*Boron doped polySi: 600-620 <sup>o</sup>C
Note: The process temperature depends vary over the furnace tube
4" furnace:
4" furnace:
*Standard polySi: 620 <sup>o</sup>C
*Standard polySi: 620 <sup>o</sup>C
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*Boron doped polySi: 620 <sup>o</sup>C
*Boron doped polySi: 620 <sup>o</sup>C
*Phosphorus doped polySi: 620 <sup>o</sup>C
*Phosphorus doped polySi: 620 <sup>o</sup>C
The process temperature depends vary over the furnace tube
The process temperature vary over the furnace tube
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|style="background:LightGrey; color:black"|Process pressure
|style="background:LightGrey; color:black"|Process pressure
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*150-250 mTorr
6" furnace:
*150-220 mTorr
4" furnace:
*250 mTorr
The process pressure depends on the actual process
The process pressure depends on the actual process
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*SiH<math>_4</math>: 50-70 sccm
*SiH<math>_4</math>: 50-70 sccm
*BCl<math>_1</math>: 1 sccm
*BCl<math>_1</math>: 1 sccm
The silane (SiH<math>_4</math>) flow depends on the actual process
4" furnace:
4" furnace:
*SiH<math>_4</math>: 80 sccm
*SiH<math>_4</math>: 80 sccm
*B<math>_2</math>H<math>_6</math>: 7 sccm
*B<math>_2</math>H<math>_6</math>: 7 sccm
*PH<math>_1</math>: 7 sccm
*PH<math>_1</math>: 7 sccm
The silane (SiH<math>_4</math>) flow depends on the actual process
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!style="background:silver; color:black" align="left" valign="top" rowspan="2"|Substrates
!style="background:silver; color:black" align="left" valign="top" rowspan="2"|Substrates
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6" furnace:
6" furnace:
*1-25 4" wafers or 6" wafers per run
*1-25 4" wafers or 6" wafers per run
4" furnace:
*1-30 4" wafers per run
*1-30 4" wafers per run
Deposition on both sides of the substrate
Deposition on both sides of the substrate
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| style="background:LightGrey; color:black"|Substrate materials allowed
| style="background:LightGrey; color:black"|Substrate materials allowed
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*Silicon wafers (new from a clean box or RCA cleaned)
*Silicon wafers (only clean wafers):
**with layers of silicon oxide or silicon (oxy)nitride
**with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned)
**from furnaces in stack A or B in cleanroom 2
*Quartz wafers (RCA cleaned)
*Quartz wafers (RCA cleaned)
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