Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using ASE/tests CHF3+H2: Difference between revisions
Jump to navigation
Jump to search
Line 283: | Line 283: | ||
|<!--'''Date'''--> 29/02/2024 | |<!--'''Date'''--> 29/02/2024 | ||
|<!--'''SEM picture'''--> [[File:Si3N4 pat3 cf4lowcp- 250.png|200px]] [[File:Si3N4 pat3 cf4lowcp- 500.png|200px]] [[File:Si3N4 pat3 cf4lowcp- 1000.png|200px]] [[File:Si3N4 pat3 cf4lowcp- 2000.png|200px]] | |<!--'''SEM picture'''--> [[File:Si3N4 pat3 cf4lowcp- 250.png|200px]] [[File:Si3N4 pat3 cf4lowcp- 500.png|200px]] [[File:Si3N4 pat3 cf4lowcp- 1000.png|200px]] [[File:Si3N4 pat3 cf4lowcp- 2000.png|200px]] | ||
|<!--'''Redeposition - top view'''--> | |<!--'''Redeposition - top view'''--> [[File:SiN cf4lowcp sidewalls 01.png|200px]] [[File:SiN cf4lowcp sidewalls 02.png|200px]] | ||
|<!--'''Etch rate in SiO2'''--> nm/min <br> +/- % | |<!--'''Etch rate in SiO2'''--> nm/min <br> +/- % | ||
|<!--'''Etch rate in resist'''--> nm/min <br> +/- % | |<!--'''Etch rate in resist'''--> nm/min <br> +/- % |
Revision as of 16:27, 18 March 2024
Tests performed with UV resist:
The tests were performed on a 100mm wafer patterned on MLA3, with 2.2um AZ5214E resist.
Tests performed with DUV resist:
The resist used was a negative DUV resist (UVN) with 915nm + 88nm BARC layer.
TEST OF TABLES DESIGN (WORK ON GOING):
SiN tests