Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using ASE/tests CHF3+H2: Difference between revisions
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|<!--'''Date'''--> 29/02/2024 | |<!--'''Date'''--> 29/02/2024 | ||
|<!--'''SEM picture'''--> [[File:Si3N4-pat1-chf3t1-250.png|250px]] [[File:Si3N4-pat1-chf3t1-500.png|250px]] [[File:Si3N4-pat1-chf3t1-1000.png|250px]] [[File:Si3N4-pat1-chf3t1-2000.png|250px]] | |<!--'''SEM picture'''--> [[File:Si3N4-pat1-chf3t1-250.png|250px]] [[File:Si3N4-pat1-chf3t1-500.png|250px]] [[File:Si3N4-pat1-chf3t1-1000.png|250px]] [[File:Si3N4-pat1-chf3t1-2000.png|250px]] | ||
|<!--'''Redeposition - | |<!--'''Redeposition- side view''--> [[File:SiN chf3.t1 sidewalls 01.png|250px]] [[File:SiN chf3.t1 sidewalls 02.png|250px]] | ||
|<!--'''Etch rate in SiO2'''--> nm/min <br> +/- % | |<!--'''Etch rate in SiO2'''--> nm/min <br> +/- % | ||
|<!--'''Etch rate in resist'''--> nm/min <br> +/- % | |<!--'''Etch rate in resist'''--> nm/min <br> +/- % |
Revision as of 16:04, 18 March 2024
Tests performed with UV resist:
The tests were performed on a 100mm wafer patterned on MLA3, with 2.2um AZ5214E resist.
Tests performed with DUV resist:
The resist used was a negative DUV resist (UVN) with 915nm + 88nm BARC layer.
TEST OF TABLES DESIGN (WORK ON GOING):
SiN tests