Specific Process Knowledge/Etch/Etching of Silicon: Difference between revisions

From LabAdviser
BGE (talk | contribs)
New page: Etch of silicon can be done by either wet etch or dry etch. The standard setups for this here at DANCHIP are: ===Wet etches:=== *KOH etch *Wet PolySilicon etch ===Dry etches:=== *Dry etch...
 
No edit summary
Line 7: Line 7:
*Dry etch using RIE1 or RIE2
*Dry etch using RIE1 or RIE2
*Dry etch using ASE
*Dry etch using ASE
==Comparison of KOH etch, wet PolySilicon etch, RIE etch and ASE etch for etching of Silicon==
{| border="1" cellspacing="0" cellpadding="5" align="center"
!
! KOH
! PolySilicon etch
! RIE
! ASE
|-
| What is it good for:
|
*Anisotropic etch in the <100>-plan
*High selectivity to the other plans
|
*Isotropic etch in Silicon and Polysilicon
|
*Can etch isotropic and anisotropic depending on the process parameters
*Anisotropic etch: vertical sidewalls independent on the crystal plans
|
*As RIE but better for high aspect ratio etching and deep etches (higher etch rate)
*Good selectivity to photoresist
|-
|
|
|
|
|
|-
|}

Revision as of 11:23, 30 October 2007

Etch of silicon can be done by either wet etch or dry etch. The standard setups for this here at DANCHIP are:

Wet etches:

  • KOH etch
  • Wet PolySilicon etch

Dry etches:

  • Dry etch using RIE1 or RIE2
  • Dry etch using ASE

Comparison of KOH etch, wet PolySilicon etch, RIE etch and ASE etch for etching of Silicon

KOH PolySilicon etch RIE ASE
What is it good for:
  • Anisotropic etch in the <100>-plan
  • High selectivity to the other plans
  • Isotropic etch in Silicon and Polysilicon
  • Can etch isotropic and anisotropic depending on the process parameters
  • Anisotropic etch: vertical sidewalls independent on the crystal plans
  • As RIE but better for high aspect ratio etching and deep etches (higher etch rate)
  • Good selectivity to photoresist