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| ==This page is under construction== | | ==This page is under construction== |
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| 1 SPTS Pegasus DRIE introduction
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| 1.1 Identification of equipment
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| 1.2 Equipment responsible
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| 1.3 Location of equipment
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| 1.4 Safety
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| 1.5 Purpose
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| The DRIE-Pegasus etch tool is a state-of-the-art silicon etch tool. The combination of advanced hardware and software enables you to either use the optimized standard processes or to tailor etch processes for your specific needs.
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| 1.6 Overview of equipment
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| Image: The load lock and MACS
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| Image: The source in the service area
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| Image: The graphical user interface
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| 2 Technical specifications
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| 2.1 Hardware summary
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| * Endpoint detection
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| * 5KW 13.56MHz RF power supply and fast acting matching unit
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| * Low notching Silicon On Insulator (SOI) capability
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| * MACS (Multiplex Atmospheric Cassette System)
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| 2.2 Wafer requirements
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| 2.3 Process parameter space
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| 2.4 Standard processes
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| 2.4.1 Process A Large trench
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| 2.4.1 Process B Via etch
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| 2.4.1 Process C Microstamp
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| 2.4.1 Process D Nanostamp
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| 3 Processing
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| 3. System control
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| Image: Description of the GUI
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| 3.1 Manual processing
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| 3.2 Automatic processing
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| 4 Recipes
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| 5 Datalogs
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| 5 Process development
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| Go to the Danchip LabAdviser page to find the most recent process development.
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| 6 User maintenance and trouble shooting
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| 6.x Pegasus acronyms
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| 8) Processing guidelines and instructions
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| 8.1) Bonding to a carrier wafer
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| 8.1.1) Why use carrier wafers
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| 8.1.2) How to bond to a carrier wafer
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| 8.1.3) Processing a bonded wafer
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| 8.2) Processing wafers with metal
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| 8.2.1) Rules for allowing metals in the ASE
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| 8.3) Recipes
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| 9) Operating instructions
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| 9.1) Processing procedure
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| 9.2) Setting the chuck temperature
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| 9.3) Loading wafers
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| 9.4) Processing
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| 9.5) The sequencer
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| 9.6) Chamber conditioning
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| 9.7) Datalogs
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| 10) User maintenance and trouble shooting
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| 10.1) Maintenance by users
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| 10.2) Trouble shooting
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| 10.3) Other information
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| 10.3.1) Training
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| 10.3.2) Literature
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| 10.3.3) ASE acronyms
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