Specific Process Knowledge/Etch/ICP Metal Etcher/Chromium: Difference between revisions

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The Chromium etch was carried out on the following substrate stack:
The Chromium etch was carried out on the following substrate stack:
2" Si wafer with Cr laying in a 6" Si wafer with a 4" recess. The area outside the recess was covered by AZ resist.
2" Si wafer with Cr laying in a 6" Si wafer with a 4" recess. The area outside the recess was covered by AZ resist.
The work was carried out be Erol Zekovic @Nanotech and BGHE@nanolab
The work was carried out by Erol Zekovic @Nanotech and BGHE@nanolab
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|+ '''Cr etch'''
|+ '''Cr etch'''
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==Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku ==  
==Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku ==  
'''This work was done by Anders Simonsen, KU''' and ''Added by bghe@Nanolab'' <br>
'''This work was done by Anders Simonsen, KU''' and ''Added by bghe@Nanolab'' <br>
Anders has done some work on optimizing the Cr etch for at 20-40 nm thick Cr that was to be used as masking for a silicon nitride etch. The Cr etch was carriered out on the ICP metal and the silicon nitride etch was done on the AOE. You can see his results in this summery that he has made:
Anders has done some work on optimizing the Cr etch for at 30 nm thick Cr that was to be used as masking for a 200nm silicon nitride etch. The Cr etch was carriered out on the ICP metal using 180 nm CSAR and the silicon nitride etch was done on the AOE. You can see his results in this summery that he has made:
* [[Media:report_summer2022 Anders Simonsen bghe edits.pdf | Cr etch development report summery by Anders Simonesen, summer of 2022 ]]
* [[Media:report_summer2022 Anders Simonsen bghe edits.pdf | Cr etch development report summery by Anders Simonesen, summer of 2022 ]]
* [[/Cr etch data from AS |Here are the raw test data and SEM images from Anders Simonsen]]
* [[/Cr etch data from AS |Here are the raw test data and SEM images from Anders Simonsen]]


'''Preferer result:'''
'''Prefered result:'''


The SEM images where done after both the Cr etch and the silicon nitride etch in the AOE using the recipe "SiN_AS". The important thing was to see how well the Cr works for masking the nitride given vertical and smooth sidewalls in the nitride. The thickness of the Cr was 40 nm   
The SEM images where done after both the Cr etch and the silicon nitride etch in the AOE using the recipe "SiN_AS". The important thing was to see how well the Cr works for masking the nitride given vertical and smooth sidewalls in the nitride. The thickness of the Cr was 40 nm   

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This page is written by Berit Herstrøm @ DTU Nanolab (BGHE) if nothing else is stated

Chromium etch in ICP metal - small substrate using carrier

The Chromium etch was carried out on the following substrate stack: 2" Si wafer with Cr laying in a 6" Si wafer with a 4" recess. The area outside the recess was covered by AZ resist. The work was carried out by Erol Zekovic @Nanotech and BGHE@nanolab

Cr etch
Parameter Cr etch
Cl2 (sccm) 65
O2 (sccm) 15
Pressure (mTorr) 15
Coil power (W) 300
Platen power (W) 15
Temperature (oC) 50
Spacers (mm) 100
Etch rate (nm/min) ~32 (Date: 2014-08-13)
Zep520A resist selectivity NA
Comment Was masked by capton tape



Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku

This work was done by Anders Simonsen, KU and Added by bghe@Nanolab
Anders has done some work on optimizing the Cr etch for at 30 nm thick Cr that was to be used as masking for a 200nm silicon nitride etch. The Cr etch was carriered out on the ICP metal using 180 nm CSAR and the silicon nitride etch was done on the AOE. You can see his results in this summery that he has made:

Prefered result:

The SEM images where done after both the Cr etch and the silicon nitride etch in the AOE using the recipe "SiN_AS". The important thing was to see how well the Cr works for masking the nitride given vertical and smooth sidewalls in the nitride. The thickness of the Cr was 40 nm

Recipe Pressure [mTorr] Coil power [W] Platen power [W] Total Flow Cl2+O2 [sccm] O2% Temp Time [s] CSAR etch rate [nm/min] CSAR rate w bond Etch rate [nm/min] Selectivity coil load coil tune plat load plat tune Comment
Cr_AS_13 10 300 15 30 23.33 20 28 100.71 42.86 0.43 This recipe was chosen over no. 12 because it did not need a large over etch of the Cr (no foot).

Recipe tried out on DUV pattern with 100 nm Cr and approx. 300 nm DUV resist

by bghe@nanolab 2022-09-29

  • A piece of approx 2cmx2cm was bonded to a Si/SiO2 wafer
  • 1 min O2 barc etch was done
  • 3min20s of CR_AS_13

Results

  • Clearly too little resist for this etch

Chromium etch in ICP metal on a thick glass substrate

The Chromium etch has ONLY been carried out on the following substrate stack: The Chromium is sputter deposited onto a 2" quartz wafer and patterned by e-beam with Zep520A resist. This 2" QZ wafer is bonded with crystal bond to a 65mmx65mm quartz plate with the thickness: 6.35mm. This QZ plate is bonded to a Si wafer.

Cr etch by bghe@nanolab
Parameter Cr etch
Cl2 (sccm) 65
O2 (sccm) 15
Pressure (mTorr) 15
Coil power (W) 300
Platen power (W) 15
Temperature (oC) 50 (no back side cooling)
Spacers (mm) 100
Etch rate (nm/min) ~14
Zep520A resist selectivity ~0.9
Comment .