Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch: Difference between revisions
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== Development of continuous nanoetch == | == Development of continuous nanoetch == | ||
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The recipes below have been run on 2" wafers with 30/60/90/120/150 nm lines in zep resist. The wafers were crystalbonded to a 4" oxide carrier leaving only a very small fraction (much less than 1% ) of silicon to be etched. If you intend to etch most of the surface of the wafer to create very small posts or ridges (rather than holes or trenches) | The recipes below have been run on 2" wafers with 30/60/90/120/150 nm lines in zep resist. The wafers were crystalbonded to a 4" oxide carrier leaving only a very small fraction (much less than 1% ) of silicon to be etched. If you intend to etch most of the surface of the wafer to create very small posts or ridges (rather than holes or trenches) | ||