Specific Process Knowledge/Etch/Etching of Bulk Glass/AOE etching of fused silica: Difference between revisions
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==Comparison of masking materials and AOE processes etching fused silica== | ==Comparison of masking materials and AOE processes etching fused silica== | ||
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|-style="background:silver; color:black" | |-style="background:silver; color:black" | ||
! | ! | ||
!AZ resist mask | !AZ resist mask (Recipe name: SiO2_res) | ||
!PolySi mask | !PolySi mask (Recipe name: SiO2_psi) | ||
!Cr mask | !Cr mask (Recipe mane: SiO2_met) | ||
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*173.5±0.5nm/min @40min etch (2013-03-13) (100nm Al on back side) | *173.5±0.5nm/min @40min etch (2013-03-13) (100nm Al on back side) | ||
*208nm/min @(5+5)min (2013-08-27) (no Al on back side, He pressure 6.8T) | *208nm/min @(5+5)min (2013-08-27) (no Al on back side, He pressure 6.8T) | ||
Reduced etch rate in long etch might be due to | ± refers to the variation over the wafer.<br> | ||
Reduced etch rate in long etch might be due to resist gone at the end. The polymer/resist left on the wafer after etch was less than 20nm and it looked burned. | |||
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*448.6±0.6nm/min @40min etch (2013-3-26) | *448.6±0.6nm/min @40min etch (2013-3-26) | ||
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<br clear="all" /> | <br clear="all" /> | ||
==User results== | ==User results== | ||
===Joachim Thomsen (student at Nanotech) October 2013=== | ===Done by Joachim Thomsen (student at Nanotech) October 2013=== | ||
process flow was: | The process flow was: | ||
*Fused silica wafers | *Fused silica wafers | ||
*Deposition of poly-Si on the wafers: LPCVD poly-Si furnace, recipe poly620, 1h30m: aprox. thickness 700nm | *Deposition of poly-Si on the wafers: LPCVD poly-Si furnace, recipe poly620, 1h30m: aprox. thickness 700nm | ||
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*Etching the poly-Si mask: AOE recipe "si_etch": 30s | *Etching the poly-Si mask: AOE recipe "si_etch": 30s | ||
*Etching the fused silica: using AOE recipe "m_polysi": 11min10sec | *Etching the fused silica: using AOE recipe "m_polysi": 11min10sec | ||
Results: | |||
<gallery caption="5 µm channels in fused silica after AOE etch - the poly-Si mask is still on" widths="200px" heights="150px" perrow="4"> | |||
image:AOE fused silica Joachim Johansen 5my channel.jpg|Profile of 5µm channel | |||
image:AOE fused silica Joachim Johansen 5my channel after quartz etch 3 002.jpg|5 µm wide channel see from above (tilted) | |||
image:AOE fused silica Joachim Thomsen 5um channel after quartz etch 5 004.jpg|channel see from above (tilted) | |||
image:AOE fused silica Joachim Thomsen 5um channel after quartz etch 9 008.jpg|Profile of 5 µm channel | |||
</gallery> |
Latest revision as of 12:34, 3 February 2023
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Comparison of masking materials and AOE processes etching fused silica
Unless otherwise stated, all content in this section was done by Berit Herstrøm, DTU Nanolab
AZ resist mask (Recipe name: SiO2_res) | PolySi mask (Recipe name: SiO2_psi) | Cr mask (Recipe mane: SiO2_met) | |
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Generel description | Using a photoresist mask as etching mask is often convenient, since it takes less process steps to make than hard masks. The draw backs using resist as masking material in the AOE on glass is that glass does not transfer heat well and therefore the He cooling in the AOE does not work well on glass substrates. This makes the photoresist turn very hot during the etch and that might burn the resist. Resist also has low selectivity to glass so deep glass etch is not working well with photoresist as masking material. | Using Poly Silicon as masking material in the AOE has the advantage over photoresist in the fact that the mask can stand a higher temperature. Then a recipe with higher etch can be used. It also as a higher selectivity so it is possible to etch deeper.The draw back might be higher line width reduction but this has not been expored yet. | This recipe with a Cr mask gives the highest etch rate, but the wafer uniformity is not so good. |
Substrate |
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Mask material/thickness |
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Pattern defined in the ICP metal |
Coil Power |
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Platen Power |
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Platen temperature |
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He flow |
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C4F8 flow |
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O2 flow |
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H2 flow |
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Pressure |
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Etch rate in fused silica |
± refers to the variation over the wafer. |
± refers to the variation over the wafer. |
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Selectivity to mask |
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Linewidth reduction |
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Substrate size tried |
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Images |
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User results
Done by Joachim Thomsen (student at Nanotech) October 2013
The process flow was:
- Fused silica wafers
- Deposition of poly-Si on the wafers: LPCVD poly-Si furnace, recipe poly620, 1h30m: aprox. thickness 700nm
- Adding AZ resist mask
- Etching the poly-Si mask: AOE recipe "si_etch": 30s
- Etching the fused silica: using AOE recipe "m_polysi": 11min10sec
Results:
- 5 µm channels in fused silica after AOE etch - the poly-Si mask is still on