Specific Process Knowledge/Etch/RIE (Reactive Ion Etch): Difference between revisions

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!style="background:silver; color:black;" align="left"|Purpose  
!style="background:silver; color:black;" align="left"|Purpose  
|style="background:LightGrey; color:black"|Deposition of dielectrica ||style="background:WhiteSmoke; color:black"|
|style="background:LightGrey; color:black"|Dry etch of ||style="background:WhiteSmoke; color:black"|
*Silicon
*Silicon oxide
*Silicon oxide
*Silicon nitride
*Silicon (oxy)nitride
*Silicon oxynitride
*PBSG (Phosphorous Boron doped Silica Glass)
*Silicon oxide doped with Germanium
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!style="background:silver; color:black" align="left"|Performance
!style="background:silver; color:black" align="left"|Performance
|style="background:LightGrey; color:black"|Film thickness||style="background:WhiteSmoke; color:black"|
|style="background:LightGrey; color:black"|Etch rates||style="background:WhiteSmoke; color:black"|
*~10nm - 30µm
*Silicon: ~0.04-0.8 µm/min
*Silicon oxide:~0.02-0.15 µm/min
*Silicon (oxy)nitride:~0.02-? µm/min
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|style="background:silver; color:black" |.||style="background:LightGrey; color:black"|Index of refraction||style="background:WhiteSmoke; color:black"|
|style="background:silver; color:black" |.||style="background:LightGrey; color:black"|Anisotropy||style="background:WhiteSmoke; color:black"|
*~1.4-2.1
*~Can vary from isotropic to anisotropic with vertical sidewalls and on to a physical etch were the sidewalls are angled but without etching under the mask.  
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|style="background:silver; color:black"|.||style="background:LightGrey; color:black"|Step coverage
|style="background:WhiteSmoke; color:black"|
*In general: Not so good
*PBSG: Floats at 1000<sup>o</sup>C
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|style="background:silver; color:black"|.||style="background:LightGrey; color:black"|Film quality
|style="background:WhiteSmoke; color:black"|
*Not so dense film
*Hydrogen will be incorporated in the films
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!style="background:silver; color:black" align="left"|Process parameter range
|style="background:LightGrey; color:black"|Process Temperature
|style="background:WhiteSmoke; color:black"|
*300 <sup>o</sup>C
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|style="background:silver; color:black"|.||style="background:LightGrey; color:black"|Process pressure
|style="background:silver; color:black"|.||style="background:LightGrey; color:black"|Process pressure
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*~200-900 mTorr
*~20-200 mTorr
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|style="background:silver; color:black"|.||style="background:LightGrey; color:black"|Gas flows
|style="background:silver; color:black"|.||style="background:LightGrey; color:black"|Gas flows
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*SiH<math>_4</math>:0-60 sccm
*SF<math>_6</math>: sccm
*N<math>_2</math>O:0-3000 sccm
*O<math>_2</math>O: sccm
*NH<math>_3</math>:0-1000 sccm
*CHF<math>_3</math>: sccm
*N<math>_2</math>:0-3000 sccm
*CF<math>_4</math>: sccm
*GeH<math>_4</math>:0-6.00 sccm
*H<math>_2</math>: sccm
*5%PH<math>_3</math>:0-99 sccm
*C<math>_2</math>F<math>_6</math>: sccm
*5%B<math>_2</math>H<math>_6</math>:0-1000 sccm
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!style="background:silver; color:black" align="left"|Substrates
!style="background:silver; color:black" align="left"|Substrates
|style="background:LightGrey; color:black"|Batch size
|style="background:LightGrey; color:black"|Batch size
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*1-3 4" wafer per run
*1 4" wafer per run
*1 6" wafer per run
*1 2" wafer per run
*Or several smaler pieces
*Or several smaller pieces
*Deposition on one side of the substrate
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|style="background:silver; color:black"|.|| style="background:LightGrey; color:black"|Substrate material allowed
|style="background:silver; color:black"|.|| style="background:LightGrey; color:black"|Substrate material allowed
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**with layers of silicon oxide or silicon (oxy)nitride
**with layers of silicon oxide or silicon (oxy)nitride
*Quartz wafers  
*Quartz wafers  
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|style="background:silver; color:black"|.|| style="background:LightGrey; color:black"|Possible masking material
|style="background:WhiteSmoke; color:black"|
*Silicon/PolySi
*Silicon oxide or silicon (oxy)nitride
*Aluminium
*Other metals if the coverage is <5% of the wafer area
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|-  
|style="background:silver; color:black"|.|| style="background:LightGrey; color:black"|Material allowed on the substrate
|style="background:silver; color:black"|.|| style="background:LightGrey; color:black"|Material allowed on the substrate

Revision as of 12:06, 5 December 2007

Etching using the dry etch technique RIE (Reactive Ion Etch)

RIE1 (part of cluster1)
RIE2 (part of cluster2)

At Danchip we have three RIE's. Two (RIE1 and RIE2) for etching silicon based materials (silicon, silicon oxide, sillicon nitride) and one (III-V RIE) for etching III-V materials (is discussed under III-V processing). The hardware of RIE1 and RIE2 is very similar but you cannot count on that identical recipes on RIE1 and RIE2 perform exactly the same. In addition to that the main difference between RIE1 and RIE2 is the cleanness of the two equipment. In rough terms RIE1 is the clean system and the RIE2 is the dirty system. This means that in RIE2 opposed to RIE1 it is allowed have small amounts of metals exposed to the plasma. Look in the manuals for RIE1 and RIE2 to read the details for this difference (you can find the manuals in LabManager [1]).

Process information


A rough overview of the performance of PECVD thin films and some process related parameters

Purpose Dry etch of
  • Silicon
  • Silicon oxide
  • Silicon (oxy)nitride
Performance Etch rates
  • Silicon: ~0.04-0.8 µm/min
  • Silicon oxide:~0.02-0.15 µm/min
  • Silicon (oxy)nitride:~0.02-? µm/min
. Anisotropy
  • ~Can vary from isotropic to anisotropic with vertical sidewalls and on to a physical etch were the sidewalls are angled but without etching under the mask.
. Process pressure
  • ~20-200 mTorr
. Gas flows
  • SF: sccm
  • OO: sccm
  • CHF: sccm
  • CF: sccm
  • H: sccm
  • CF: sccm
Substrates Batch size
  • 1 4" wafer per run
  • 1 2" wafer per run
  • Or several smaller pieces
. Substrate material allowed
  • Silicon wafers
    • with layers of silicon oxide or silicon (oxy)nitride
  • Quartz wafers
. Possible masking material
  • Silicon/PolySi
  • Silicon oxide or silicon (oxy)nitride
  • Aluminium
  • Other metals if the coverage is <5% of the wafer area
. Material allowed on the substrate
  • Aluminium
  • All metals < 5% of the substrate coverage (ONLY PECVD3!)