Specific Process Knowledge/Etch/ICP Metal Etcher/Chromium: Difference between revisions

From LabAdviser
BGE (talk | contribs)
Bghe (talk | contribs)
 
(39 intermediate revisions by 2 users not shown)
Line 1: Line 1:
'''Feedback to this page''': '''[mailto:plasma@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.danchip.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/Chromium click here]'''  
'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/Chromium click here]'''  
<br> {{CC-bghe1}}


==Chromium etch in ICP metal - small substrate using carrier==
The Chromium etch was carried out on the following substrate stack:
2" Si wafer with Cr laying in a 6" Si wafer with a 4" recess. The area outside the recess was covered by AZ resist.
The work was carried out by Erol Zekovic @Nanotech and BGHE@nanolab
{| border="2" cellpadding="2" cellspacing="1" style="text-align:center;"
|+ '''Cr etch'''
|-
! Parameter
|'''Cr etch'''
|-
! Cl<sub>2</sub> (sccm)
| 65
|-
! O<sub>2</sub> (sccm)
| 15
|-
! Pressure (mTorr)
| 15
|-
! Coil power (W)
| 300
|-
! Platen power (W)
| 15
|-
! Temperature (<sup>o</sup>C)
| 50
|-
! Spacers (mm)
| 100
|-
! Etch rate (nm/min)
| ~32 (Date: 2014-08-13)
|-
!Zep520A resist selectivity
| NA
|-
!Comment
| Was masked by capton tape
|}
<gallery caption="Etching lines in 100nm Cr with the Cr etch for 3 min with 300 nm DUV resist ''BGHE@Nanolab Feb 2022''" perrow="5" widths="400px" heights="300px">
Image:S036039pro_34.jpg
Image:S036039top_18.jpg
Image:S03603906.jpg
Image:S03603910.jpg
Image:S03603912.jpg
</gallery>
<gallery caption="Etching lines in 100nm Cr with the Cr etch for 3:20 min with pressure of 30 mTorr and 20C with 300 nm DUV resist ''BGHE@Nanolab Oct 2022''" perrow="5" widths="400px" heights="300px">
Image:S03385207.jpg
Image:S03385211.jpg
Image:S03385213.jpg
Image:S03385204.jpg
Image:S03385215.jpg
</gallery>
<br>
==Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku ==
'''This work was done by Anders Simonsen, KU''' and ''Added by bghe@Nanolab'' <br>
Anders has done some work on optimizing the Cr etch for at 30 nm thick Cr that was to be used as masking for a 200nm silicon nitride etch. The Cr etch was carriered out on the ICP metal using 180 nm CSAR and the silicon nitride etch was done on the AOE. You can see his results in this summery that he has made:
* [[Media:report_summer2022 Anders Simonsen bghe edits.pdf | Cr etch development report summery by Anders Simonesen, summer of 2022 ]]
* [[/Cr etch data from AS |Here are the raw test data and SEM images from Anders Simonsen]]
'''Prefered result:'''
The SEM images where done after both the Cr etch and the silicon nitride etch in the AOE using the recipe "SiN_AS". The important thing was to see how well the Cr works for masking the nitride given vertical and smooth sidewalls in the nitride. The thickness of the Cr was 40 nm 
{| class="wikitable"
! Recipe !! Pressure [mTorr] !! Coil power [W] !! Platen power [W] !! Total Flow Cl2+O2 [sccm] !! O2% !! Temp !!  !! Time [s] !! CSAR etch rate [nm/min] !! CSAR rate w bond !!  !! Etch rate [nm/min] !! Selectivity !!  !! coil load !! coil tune !! plat load !! plat tune !! Comment
|-
! Cr_AS_13
| 10 || 300 || 15 || 30 || 23.33 || 20 ||  || 28 || 100.71 ||  ||  || 42.86 || 0.43 ||  ||  ||  ||  ||  || This recipe was chosen over no. 12 because it did not need a large over etch of the Cr (no foot).
|-
|}
<gallery caption="After Cr etch with recipe 13 and nitride etch in the AOE 20s" widths="400px" heights="300px" perrow="2">
Image:Cr-75s_sin-met-20s_0733.jpg| 75s Cr etch
Image:Cr-90s_sin-met-20s_0757.jpg| 90s Cr etch
</gallery>
=== Recipe tried out on DUV pattern with 100 nm Cr and approx. 300 nm DUV resist===
''by bghe@nanolab 2022-09-29''
* A piece of approx 2cmx2cm was bonded to a Si/SiO2 wafer
*1 min O2 barc etch was done
*3min20s of CR_AS_13
====Results====
*Clearly too little resist for this etch
<gallery caption="After Cr etch with recipe Cr_AS_13 for 3min20s" widths="300px" heights="225px" perrow="4">
Image:S0338_51_05.jpg
Image:S0338_51_06.jpg
Image:S0338_51_01.jpg
Image:S0338_51_03.jpg
Image:S0338_51_04.jpg
Image:S0338_51_00.jpg
Image:S0338_51_07.jpg
</gallery>


===Chromium etch in ICP metal===
==Chromium etch in ICP metal on a thick glass substrate==
The Chromium etch has ONLY been carried out on the following substrate stack:
The Chromium etch has ONLY been carried out on the following substrate stack:
The Chromium is sputter deposited onto a 2" quartz wafer and pattered by e-beam with Zep520A resist.
The Chromium is sputter deposited onto a 2" quartz wafer and patterned by e-beam with Zep520A resist.
This 2" QZ wafer is bonded with crystal bond to a 65mmx65mm quartz plate with the thickness: 6.35mm.
This 2" QZ wafer is bonded with crystal bond to a 65mmx65mm quartz plate with the thickness: 6.35mm.
This QZ plate is bonded to a Si wafer.
This QZ plate is bonded to a Si wafer.
{| border="2" cellpadding="2" cellspacing="1" style="text-align:center;"
{| border="2" cellpadding="2" cellspacing="1" style="text-align:center;"
|+ '''Cr etch''' by bghe@danchip
|+ '''Cr etch''' by bghe@nanolab
|-
|-
! Parameter
! Parameter

Latest revision as of 12:22, 26 July 2023

Feedback to this page: click here
This page is written by Berit Herstrøm @ DTU Nanolab (BGHE) if nothing else is stated

Chromium etch in ICP metal - small substrate using carrier

The Chromium etch was carried out on the following substrate stack: 2" Si wafer with Cr laying in a 6" Si wafer with a 4" recess. The area outside the recess was covered by AZ resist. The work was carried out by Erol Zekovic @Nanotech and BGHE@nanolab

Cr etch
Parameter Cr etch
Cl2 (sccm) 65
O2 (sccm) 15
Pressure (mTorr) 15
Coil power (W) 300
Platen power (W) 15
Temperature (oC) 50
Spacers (mm) 100
Etch rate (nm/min) ~32 (Date: 2014-08-13)
Zep520A resist selectivity NA
Comment Was masked by capton tape



Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku

This work was done by Anders Simonsen, KU and Added by bghe@Nanolab
Anders has done some work on optimizing the Cr etch for at 30 nm thick Cr that was to be used as masking for a 200nm silicon nitride etch. The Cr etch was carriered out on the ICP metal using 180 nm CSAR and the silicon nitride etch was done on the AOE. You can see his results in this summery that he has made:

Prefered result:

The SEM images where done after both the Cr etch and the silicon nitride etch in the AOE using the recipe "SiN_AS". The important thing was to see how well the Cr works for masking the nitride given vertical and smooth sidewalls in the nitride. The thickness of the Cr was 40 nm

Recipe Pressure [mTorr] Coil power [W] Platen power [W] Total Flow Cl2+O2 [sccm] O2% Temp Time [s] CSAR etch rate [nm/min] CSAR rate w bond Etch rate [nm/min] Selectivity coil load coil tune plat load plat tune Comment
Cr_AS_13 10 300 15 30 23.33 20 28 100.71 42.86 0.43 This recipe was chosen over no. 12 because it did not need a large over etch of the Cr (no foot).

Recipe tried out on DUV pattern with 100 nm Cr and approx. 300 nm DUV resist

by bghe@nanolab 2022-09-29

  • A piece of approx 2cmx2cm was bonded to a Si/SiO2 wafer
  • 1 min O2 barc etch was done
  • 3min20s of CR_AS_13

Results

  • Clearly too little resist for this etch

Chromium etch in ICP metal on a thick glass substrate

The Chromium etch has ONLY been carried out on the following substrate stack: The Chromium is sputter deposited onto a 2" quartz wafer and patterned by e-beam with Zep520A resist. This 2" QZ wafer is bonded with crystal bond to a 65mmx65mm quartz plate with the thickness: 6.35mm. This QZ plate is bonded to a Si wafer.

Cr etch by bghe@nanolab
Parameter Cr etch
Cl2 (sccm) 65
O2 (sccm) 15
Pressure (mTorr) 15
Coil power (W) 300
Platen power (W) 15
Temperature (oC) 50 (no back side cooling)
Spacers (mm) 100
Etch rate (nm/min) ~14
Zep520A resist selectivity ~0.9
Comment .