Specific Process Knowledge/Thin film deposition/Deposition of Silicon Oxide/IBSD of SiO2: Difference between revisions

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'''Acceptance test for SiO2 deposition:'''
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[[Specific Process Knowledge/Etch/IBE&frasl;IBSD Ionfab 300|Go to 'IBE/IBSD Ionfab 300' equipment page]]
 
 
==Acceptance test for SiO2 deposition (2011) on IBE/IBSD Ionfab 300+)==
{| border="2" cellspacing="0" cellpadding="2"  
{| border="2" cellspacing="0" cellpadding="2"  
|-
|-
Line 13: Line 20:
*50 mm SSP Si wafer
*50 mm SSP Si wafer
*525 µm thick
*525 µm thick
*Supplied by Danchip
*Supplied by Nanolab
|
|
*100 mm SSP Si wafer
*100 mm SSP Si wafer
Line 25: Line 32:
*SiO2
*SiO2
The purpose of the SiO2 is to be part of a mirror: <br\>
The purpose of the SiO2 is to be part of a mirror: <br\>
5 quarterwavelength pairs of <br\>
5 quarter wavelength pairs of <br\>
SiO2 <br\>
SiO2 <br\>
TiO2 <br\>
TiO2 <br\>
Extra quarterwavelength layer of <br\>
Extra quarter wavelength layer of <br\>
TiO2 <br\>
TiO2 <br\>
5 quarterwavelength pairs of <br\>
5 quarter wavelength pairs of <br\>
SiO2 <br\>
SiO2 <br\>
TiO2 <br\>
TiO2 <br\>
Line 43: Line 50:
!style="background:silver; color:black" align="left" valign="top"|Deposition thickness
!style="background:silver; color:black" align="left" valign="top"|Deposition thickness
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*222nm
*222 nm
|
|
*~215nm
*~215 nm
|
|
*224nm
*224nm
Line 53: Line 60:
*6 nm/min
*6 nm/min
|
|
*7.42nm/min +- 0.04nm/min  
*7.42 nm/min +- 0.04nm/min  
One standard deviation
One standard deviation
|
|
*7.73nm/min
*7.73 nm/min
Only made once
Only made once
|-
|-
Line 77: Line 84:
!style="background:silver; color:black" align="left" valign="top"|Stress
!style="background:silver; color:black" align="left" valign="top"|Stress
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*<500MPa
*<500 MPa
|
|
*~600MPa
*~600 MPa
|
|
*475MPa
*475 MPa
|-
!style="background:silver; color:black" align="left" valign="top"|Refractive index
|style="background:WhiteSmoke; color:black"|.
|
*1.490+-0.004 (stddev wafer to wafer)
|
*1.482+-0.002 (stddev on wafer)
|-
|}
 
 
{| border="2" cellspacing="1" cellpadding="3" align="left"
!
!Recipe 1
!Recipe 2
|-
|Platen angle
|15 degrees
|10 degrees
|-
|Platen rotation speed
|20 rpm
|20 rpm
|-
|Ar(N) flow
|4 sccm
|4 sccm
|-
|Ar(dep. source) flow
|9 sccm
|8 sccm
|-
|I(N)
|310 mA
|320 mA
|-
|Power
|675 W
|700 W
|-
|I(B)
|310 mA
|280 mA
|-
|V(B)
|1200 V
|1100 V
|-
|Vacc(B)
|400 V
|400 V
|-
|Deposition time
|29 min
|37 min
|-
|}
|}
<br clear="all" />
==Other results==
===Roughness of the surface===
Measured with the Optical profiler - PSI mode (on one sample from the acceptance test): Sa= 0.6 nm
===Uniformity and break down voltage ''by Mathias Engholm 2016-11-29''===
Mathias made 105.62nm SiO2 on a test silicon wafer and on his sample wafer. The sample wafer had gold/Cr on the surface and that had to be electrically isolated. The uniformity over the wafer of the oxide was 0.19% over 9 points - this is better than he has achieved when oxidizing in a furnace. He anodic bonded the wafer without problems. He measured the breakdown voltage and got 0.82+/+ 0.13 V/nm over 24 points. This is just as good as the oxide from the furnaces. Before his deposition he ran a 20 min heat up and 40min dummy deposition to clean the target. This was done with a bright new target and with the small deposition grids mounted.<br>
[[File:breakdownvoltage.png|thumb|left|400px| Breakdown voltage over the wafer, ''by Mathias Engholm 2016-11-29'']]
[[File:Ibsd uniformity SiO2.jpg|thumb|none|500px| Thickness uniformity over the wafer, ''by Mathias Engholm 2016-11-29'']]<br>

Latest revision as of 11:56, 24 March 2023

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Go to 'IBE/IBSD Ionfab 300' equipment page


Acceptance test for SiO2 deposition (2011) on IBE/IBSD Ionfab 300+)

. Acceptance Criteria

Acceptance Result 1

Acceptance Result 2

Substrate information
  • 50 mm SSP Si wafer
  • 525 µm thick
  • Supplied by Nanolab
  • 100 mm SSP Si wafer
  • 525+-25 µm thick
  • 100 mm SSP Si wafer
  • 525+-25 µm thick
Material to be deposited
  • SiO2

The purpose of the SiO2 is to be part of a mirror: <br\> 5 quarter wavelength pairs of <br\> SiO2 <br\> TiO2 <br\> Extra quarter wavelength layer of <br\> TiO2 <br\> 5 quarter wavelength pairs of <br\> SiO2 <br\> TiO2 <br\> Design wavelength (for refractive indices and layer thicknesses): 1300nm <br\> The acceptance criteria is set up for the single SiO2 and TiO2 layers. <br\> Five runs in a row for each material.

  • SiO2
  • SiO2
Deposition thickness
  • 222 nm
  • ~215 nm
  • 224nm
Deposition rate
  • 6 nm/min
  • 7.42 nm/min +- 0.04nm/min

One standard deviation

  • 7.73 nm/min

Only made once

Thickness uniformity
  • <+-1%
  • +-(0.46% +-0.10%)
  • +-0.45%
Reproducibility
  • <+-1.5%
  • +-0.6%
  • Not measured
Stress
  • <500 MPa
  • ~600 MPa
  • 475 MPa
Refractive index .
  • 1.490+-0.004 (stddev wafer to wafer)
  • 1.482+-0.002 (stddev on wafer)


Recipe 1 Recipe 2
Platen angle 15 degrees 10 degrees
Platen rotation speed 20 rpm 20 rpm
Ar(N) flow 4 sccm 4 sccm
Ar(dep. source) flow 9 sccm 8 sccm
I(N) 310 mA 320 mA
Power 675 W 700 W
I(B) 310 mA 280 mA
V(B) 1200 V 1100 V
Vacc(B) 400 V 400 V
Deposition time 29 min 37 min


Other results

Roughness of the surface

Measured with the Optical profiler - PSI mode (on one sample from the acceptance test): Sa= 0.6 nm

Uniformity and break down voltage by Mathias Engholm 2016-11-29

Mathias made 105.62nm SiO2 on a test silicon wafer and on his sample wafer. The sample wafer had gold/Cr on the surface and that had to be electrically isolated. The uniformity over the wafer of the oxide was 0.19% over 9 points - this is better than he has achieved when oxidizing in a furnace. He anodic bonded the wafer without problems. He measured the breakdown voltage and got 0.82+/+ 0.13 V/nm over 24 points. This is just as good as the oxide from the furnaces. Before his deposition he ran a 20 min heat up and 40min dummy deposition to clean the target. This was done with a bright new target and with the small deposition grids mounted.

Breakdown voltage over the wafer, by Mathias Engholm 2016-11-29
Thickness uniformity over the wafer, by Mathias Engholm 2016-11-29