Specific Process Knowledge/Bonding: Difference between revisions
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'''Feedback to this page''': '''[mailto:labadviser@ | '''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Bonding click here]''' | ||
'''Unless anything else is stated, everything on this page, text and pictures are made by DTU Nanolab.''' | |||
For bonding samples to a carrier wafer in order to enable '''dry etching''', please go [[Specific_Process_Knowledge/Etch/DryEtchProcessing/Bonding|here]]. | |||
For bonding samples to a carrier wafer for '''UV-lithography''' using automatic coater and developer, please see this process flow: [[media:Process_Flow_ChipOnCarrier.docx|Process_Flow_ChipOnCarrier.docx]], and refer to the [[Specific_Process_Knowledge/Etch/DryEtchProcessing/Bonding#Bonding|bonding procedure]] for dry etching. | |||
== Choose equipment == | == Choose equipment == | ||
*[[/ | *[[/Imprinter 02|Imprinter 02]] | ||
*[[/Wafer Bonder 02|Wafer Bonder 02]] | |||
*[[Specific Process Knowledge/Thermal Process/C3 Anneal-bond furnace|C3 furnace anneal bond]] | *[[Specific Process Knowledge/Thermal Process/C3 Anneal-bond furnace|C3 furnace anneal bond]] | ||
== Choose bonding methods in | == Choose bonding methods in Wafer Bonder 2 == | ||
*[[/Eutectic bonding|Eutectic bonding]] | *[[/Eutectic bonding|Eutectic bonding]] | ||
| Line 12: | Line 18: | ||
*[[/Anodic bonding|Anodic bonding]] | *[[/Anodic bonding|Anodic bonding]] | ||
== Comparing the three bonding methods in the | == Comparing the three bonding methods in the wafer bonder 2 == | ||
{| border="2" cellspacing="0" cellpadding="2" | {| border="2" cellspacing="0" cellpadding="2" | ||
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!Bonding temperature | !Bonding temperature | ||
|Depending on the eutecticum 310°C to 400°C. | |Depending on the eutecticum 310°C to 400°C. | ||
|Depending on defects 50°C to 400°C. | |Depending on defects 50°C to 400°C. | ||
|Depending on the voltage 300°C to 500°C Standard is 400°C. | |Depending on the voltage 300°C to 500°C Standard is 400°C. | ||
|- | |- | ||
| Line 40: | Line 46: | ||
!Annealing temperature | !Annealing temperature | ||
|No annealing | |No annealing | ||
|1000°C in the bond furnace C3. | |1000°C-1100°C in the anneal bond furnace (C3). | ||
|No annealing | |No annealing | ||
|- | |- | ||
| Line 53: | Line 59: | ||
|-style="background:WhiteSmoke; color:black" | |-style="background:WhiteSmoke; color:black" | ||
!Substrate size | !Substrate size | ||
|Up to | |Up to 4" | ||
|Up to | |Up to 4" | ||
|Up to | |Up to 4" | ||
|- | |- | ||
| Line 66: | Line 72: | ||
|-style="background:WhiteSmoke; color:black" | |-style="background:WhiteSmoke; color:black" | ||
! | !Backside alignment | ||
|Double side polished wafers. | |Double side polished wafers. | ||
|Double side polished wafers. | |Double side polished wafers. | ||
Latest revision as of 07:18, 6 February 2023
Feedback to this page: click here
Unless anything else is stated, everything on this page, text and pictures are made by DTU Nanolab.
For bonding samples to a carrier wafer in order to enable dry etching, please go here.
For bonding samples to a carrier wafer for UV-lithography using automatic coater and developer, please see this process flow: Process_Flow_ChipOnCarrier.docx, and refer to the bonding procedure for dry etching.
Choose equipment
Choose bonding methods in Wafer Bonder 2
Comparing the three bonding methods in the wafer bonder 2
| Eutectic bonding | Fusion bonding | Anodic bonding | |
|---|---|---|---|
| General description | For bonding two substrates by use of an interphase that makes an eutecticum. | For bonding two identical materials. | For bonding Si and Glass. |
| Bonding temperature | Depending on the eutecticum 310°C to 400°C. | Depending on defects 50°C to 400°C. | Depending on the voltage 300°C to 500°C Standard is 400°C. |
| Annealing temperature | No annealing | 1000°C-1100°C in the anneal bond furnace (C3). | No annealing |
| Materials possible to bond | Bonding of substrates is done by use of the eutectica Au/Si, Au/Sn and Au/Sn/Ni | Si/Si, SiO2/SiO2 | Si/Pyrex (glass) |
| Substrate size | Up to 4" | Up to 4" | Up to 4" |
| Cleaning | Cleaning by N2. | Wet chemical cleaning, IMEC. | Cleaning by N2. |
| Backside alignment | Double side polished wafers. | Double side polished wafers. | Not relevant. |