Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE/Standard recipe with resist mask/SiO2 etch with DUV mask

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This page is written by Berit Herstrøm @ DTU Nanolab (BGHE) if nothing else is stated

• Etch of Thermal silicon oxide with DUV KRF resist as mask. Made by BGHE@Nanolab February 2015
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  Profile of SiO2 lines etched for 5min with SiO2_res in the AOE

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  Profile of SiO2 lines etched for 5min with SiO2_res in the AOE, vertical sidewalls, 1µm pitch

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  Profile of SiO2 lines etched for 5min with SiO2_res in the AOE, vertical sidewalls, 4µm pitch

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  Bird view of 1µm pitch SiO2 lines, some roughness is seem.

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  Profile of SiO2 lines etched for 5min with SiO2_res in the AOE, all resist is gone and it has been etched a little down in the Si.

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  Profile of SiO2 lines etched for 5min with SiO2_res in the AOE, all resist is gone and it has been etched a little down in the Si.